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Exact memory size estimation for array computations without loop unrolling

Authors:

Ying Zhao,

Sharad MalikAuthors Info & Claims

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Pages 811 - 816

https://doi.org/10.1145/309847.310074

Published: 01 June 1999 Publication History

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Cited By

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An LYang G(2020)Adaptive Secure State Estimation for Cyber-Physical Systems With Low Memory CostIEEE Transactions on Control of Network Systems10.1109/TCNS.2020.29882457:4(1621-1632)Online publication date: Dec-2020
https://doi.org/10.1109/TCNS.2020.2988245
Sharma NPanda PCatthoor FRaghavan PAa T(2015)Array Interleaving—An Energy-Efficient Data Layout TransformationACM Transactions on Design Automation of Electronic Systems10.1145/274787520:3(1-26)Online publication date: 24-Jun-2015
https://dl.acm.org/doi/10.1145/2747875
Bohnert MScholl C(2014)A dynamic virtual memory management under real-time constraints2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications10.1109/RTCSA.2014.6910522(1-10)Online publication date: Aug-2014
https://doi.org/10.1109/RTCSA.2014.6910522
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Exact memory size estimation for array computations without loop unrolling
1. Hardware

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Exact memory size estimation for array computations
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Published In

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

June 1999

1000 pages

ISBN:1581131097

DOI:10.1145/309847

Editor:
Mary Jane Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1999

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DAC99

Sponsor:

EDAC
SIGDA
IEEE-CAS

DAC99: The 36th ACM/IEEE-CAS/EDAC Design Automation Conference

June 21 - 25, 1999

Louisiana, New Orleans, USA

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DAC '99 Paper Acceptance Rate 154 of 451 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Cited By

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An LYang G(2020)Adaptive Secure State Estimation for Cyber-Physical Systems With Low Memory CostIEEE Transactions on Control of Network Systems10.1109/TCNS.2020.29882457:4(1621-1632)Online publication date: Dec-2020
https://doi.org/10.1109/TCNS.2020.2988245
Sharma NPanda PCatthoor FRaghavan PAa T(2015)Array Interleaving—An Energy-Efficient Data Layout TransformationACM Transactions on Design Automation of Electronic Systems10.1145/274787520:3(1-26)Online publication date: 24-Jun-2015
https://dl.acm.org/doi/10.1145/2747875
Bohnert MScholl C(2014)A dynamic virtual memory management under real-time constraints2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications10.1109/RTCSA.2014.6910522(1-10)Online publication date: Aug-2014
https://doi.org/10.1109/RTCSA.2014.6910522
Ma HDiersen SWang LLiao CQuinlan DYang Z(2013)Symbolic Analysis of Concurrency Errors in OpenMP ProgramsProceedings of the 2013 42nd International Conference on Parallel Processing10.1109/ICPP.2013.63(510-516)Online publication date: 1-Oct-2013
https://dl.acm.org/doi/10.1109/ICPP.2013.63
Ozturk O(2011)Data locality and parallelism optimization using a constraint-based approachJournal of Parallel and Distributed Computing10.1016/j.jpdc.2010.08.00571:2(280-287)Online publication date: 1-Feb-2011
https://dl.acm.org/doi/10.1016/j.jpdc.2010.08.005
Philippidis CShang W(2010)On minimizing register usage of linearly scheduled algorithms with uniform dependenciesComputer Languages, Systems and Structures10.1016/j.cl.2009.12.00136:3(250-267)Online publication date: 1-Oct-2010
https://dl.acm.org/doi/10.1016/j.cl.2009.12.001
C SV G(2009)A Novel Approach for Estimation and Optimization of Memory In Low Power Embedded SystemsInternational Journal of Computer Theory and Engineering10.7763/IJCTE.2009.V1.93(581-587)Online publication date: 2009
https://doi.org/10.7763/IJCTE.2009.V1.93
Unnikrishnan PChen GKandemir MKarakoy MKolcu I(2009)Reducing memory requirements of resource-constrained applicationsACM Transactions on Embedded Computing Systems10.1145/1509288.15092898:3(1-37)Online publication date: 22-Apr-2009
https://dl.acm.org/doi/10.1145/1509288.1509289
Baskaran MBondhugula UKrishnamoorthy SRamanujam JRountev ASadayappan PChatterjee SScott M(2008)Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memoriesProceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming10.1145/1345206.1345210(1-10)Online publication date: 20-Feb-2008
https://dl.acm.org/doi/10.1145/1345206.1345210
Kjeldsberg PCatthoor FVerdoolaege SPalkovic MVandecappelle AHu QAas E(2008)Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing ApplicationsJournal of Signal Processing Systems10.1007/s11265-008-0178-653:3(301-321)Online publication date: 1-Dec-2008
https://dl.acm.org/doi/10.1007/s11265-008-0178-6
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