research-article

Exploring fast and slow memories in HMP core types: work-in-progress

Authors:

Bryan Donyanavard,

Amir Mahdi Hosseini Monazzah,

Nikil DuttAuthors Info & Claims

CODES '17: Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion

Article No.: 4, Pages 1 - 2

https://doi.org/10.1145/3125502.3125545

Published: 15 October 2017 Publication History

Abstract

Studies have shown memory and computational needs vary independently across applications. Recent work has explored using hybrid memory technology (SRAM+NVM) in on-chip memories of multicore processors (CMPs) to support the varied needs of diverse workloads. Such works suggest architectural modifications that require supplemental management in the memory hierarchy. Instead, we propose to deploy hybrid memory in a manner that integrates seamlessly with the existing heterogeneous multicore (HMP) architectural model, and therefore does not require any architectural modification, simply the integration of different memory technologies on-chip. We evaluate platforms with a combination of fast (SRAM cache) and slow (STT-MRAM cache) core-types for mobile workloads.

References

[1]

ARM. 2013. big. UTILE Technology: The Future of Mobile. Technical Report. ARM. 1--12 pages.

[2]

Christian Bienia. 2011. Benchmarking Modern Multiprocessors. Ph.D. Dissertation. Princeton University.

[3]

X. Chen, N. Khoshavi, R. F. DeMara. J. Wang, D. Huang, W. Wen, and Y. Chen. 2017. Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache. IEEE Trans. Comput. 66. 5 (May 2017), 786--798.

Digital Library

[4]

J. Choi and G. H. Park. 2017. NVM Way Allocation Scheme to Reduce NVM Writes for Hybrid Cache Architecture in Chip-Multiprocessors. IEEE Transactions on Parallel and Distributed Systems PP, 99 (2017), 1--1.

[5]

ARM Cortex. 2011. A15. Technical Reference Manual (2011).

[6]

X. Dong, C. Xu, Y. Xie, and N. P. Jouppi. 2012. NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, 7 (July 2012), 994--1007.

Digital Library

[7]

Matthew R Guthaus, Jeffrey S Ringenberg, Dan Ernst, Todd M Austin, Trevor Mudge, and Richard B Brown. 2001. MiBench : A free, commercially representative embedded benchmark suite. In IEEE 4th Annual Workshop on Workload Characterization.

[8]

J. Hu, C. J. Xue, Q. Zhuge, W. C. Tseng, and E. H. M. Sha. 2011. Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory. In 2011 Design, Automation Test in Europe. 1--6.

[9]

H. Kim, S. Kim, and J. Lee. 2017. Write-Amount-Aware Management Policies for STT-RAM Caches. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, 4 (April 2017), 1588--1592.

Digital Library

[10]

J. Li, C. J. Xue, and Yinlong Xu. 2011. STT-RAM based energy-efficiency hybrid cache for CMPs. In 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip. 31--36.

[11]

A. M. H. Monazzah, H. Farben, S. G. Miremadi, M. Fazeli, and H. Asadi. 2013. FTSPM: A Fault-Tolerant Scratchpad Memory. In 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN). 1--10.

Digital Library

[12]

F. Oboril, R. Bishnoi, M. Ebrahimi, and M. B. Tahoori. 2015. Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, 3 (March 2015), 367--380.

[13]

S. Senni, T. Delobelle, O. Coi, P. Y. Peneau, L. Torres, A. Gamatie, P. Benoit, and G. Sassatelli. 2017. Embedded systems to high performance computing using STT-MRAM. In Design, Automation Test in Europe Conference Exhibition (DATE), 2017. 536--541.

[14]

J. Wang, Y. Tim, W. F. Wong, Z. L. Ong, Z. Sun, and H. H. Li. 2014. A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores. In 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC). 610--615.

[15]

Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ram Rajamony, and Yuan Xie. 2009. Hybrid Cache Architecture with Disparate Memory Technologies. In Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA '09).

Digital Library

Cited By

Donvanavard BMonazzah ADutt NMuck T(2018)Exploring Hybrid Memory Caches in Chip Multiprocessors2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2018.8449386(1-8)Online publication date: Jul-2018
https://doi.org/10.1109/ReCoSoC.2018.8449386

Recommendations

ShaVe-ICE: Sharing Distributed Virtualized SPMs in Many-Core Embedded Systems
Special Issue on MEMCODE 2015 and Regular Papers (Diamonds)

Traditional approaches for managing software-programmable memories (SPMs) do not support sharing of distributed on-chip memory resources and, consequently, miss the opportunity to better utilize those memory resources. Managing on-chip memory resources ...
Scratchpad-Memory Management for Multi-Threaded Applications on Many-Core Architectures
Special Issue on MEMOCODE 2017 and Regular Papers

Contemporary many-core architectures, such as Adapteva Epiphany and Sunway TaihuLight, employ per-core software-controlled Scratchpad Memory (SPM) rather than caches for better performance-per-watt and predictability. In these architectures, a core is ...
Write activity reduction on non-volatile main memories for embedded chip multiprocessors

Recent advances in circuit and semiconductor technologies have pushed Non-Volatile Memory (NVM) technologies into a new era. These technologies exhibit appealing properties such as low power consumption, non-volatility, shock-resistivity, and high ...

Comments

Information & Contributors

Information

Published In

cover image ACM Other conferences

CODES '17: Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion

October 2017

84 pages

ISBN:9781450351850

DOI:10.1145/3125502

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 October 2017

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

ESWEEK'17

ESWEEK'17: THIRTEENTH EMBEDDED SYSTEM WEEK

October 15 - 20, 2017

Seoul, Republic of Korea

Acceptance Rates

Overall Acceptance Rate 280 of 864 submissions, 32%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

1
Total Citations
View Citations
83
Total Downloads

Downloads (Last 12 months)1
Downloads (Last 6 weeks)1

Reflects downloads up to 30 Aug 2024

Other Metrics

View Author Metrics

Citations

Cited By

Donvanavard BMonazzah ADutt NMuck T(2018)Exploring Hybrid Memory Caches in Chip Multiprocessors2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC.2018.8449386(1-8)Online publication date: Jul-2018
https://doi.org/10.1109/ReCoSoC.2018.8449386

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents