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Modeling and Validation of a Mixed-Criticality NoC Router Using the IF Language

Published: 14 October 2017 Publication History

Abstract

In Mixed-Criticality Systems (MCS), high-critical real-time and low-critical real-time applications share the same hardware platform. Today MCS must also be implementable on NoC-based architectures. Those applications exchange messages with different timing requirements through the same network. Sharing resources between flows in a NoC can lead to unpredictable latencies and subsequently complicate the implementation of MCS in many-core architectures. A solution is that NoC routers provide guarantees for high-critical communications with a minimum impact on performances for low-critical communications. We propose a new router called DAS, which exhibits such properties to support MCS applications. Moreover we introduce the first formal verification of the MCS properties of a NoC-router. We detail a formal specification of the DAS router, with the IF language, in order to verify its ability to support MCS applications. We also describe the validation approach of this specification based on those properties and using the IF toolset.

References

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M. Bozga, S. Graf, and L. Mounier. IF-2.0: A Validation Environment for Component-Based Real-Time Systems. In Proceedings of CAV'02, pages 343--348, London, UK, 2002. Springer-Verlag.
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M. Bozga, S. Graf, I. Ober, and J. Sifakis. The IF toolset. In SFM-04, volume 3185 of LNCS, pages 237--267. Springer-Verlag, June 2004.
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A. Burns and R. Davis. Mixed criticality systems-a review, 9th ed. Technical report, Department of Computer Science, University of York, Jan 2017. http://www-users.cs.york.ac.uk/burns/review.pdf.
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M. Dridi, S. Rubini, M. Lallali, M. Johanna, F. Singhoff, and J.-P. Diguet. Das: an efficient noc router for mixed-criticality real-time systems. In 2017 IEEE International Conference on Computer Design, November 2017.
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Cited By

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  • (2022)Scaling Up Livelock Verification for Network-on-Chip Routing AlgorithmsVerification, Model Checking, and Abstract Interpretation10.1007/978-3-030-94583-1_19(378-399)Online publication date: 16-Jan-2022
  • (2019)Design and Multi-Abstraction-Level Evaluation of a NoC Router for Mixed-Criticality Real-Time SystemsACM Journal on Emerging Technologies in Computing Systems10.1145/326481815:1(1-37)Online publication date: 14-Feb-2019
  • (2017)DAS: An Efficient NoC Router for Mixed-Criticality Real-Time Systems2017 IEEE International Conference on Computer Design (ICCD)10.1109/ICCD.2017.42(229-232)Online publication date: Nov-2017

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cover image ACM Conferences
NoCArc '17: Proceedings of the 10th International Workshop on Network on Chip Architectures
October 2017
63 pages
ISBN:9781450355421
DOI:10.1145/3139540
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Published: 14 October 2017

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NoCArc '17 Paper Acceptance Rate 6 of 20 submissions, 30%;
Overall Acceptance Rate 46 of 122 submissions, 38%

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Cited By

View all
  • (2022)Scaling Up Livelock Verification for Network-on-Chip Routing AlgorithmsVerification, Model Checking, and Abstract Interpretation10.1007/978-3-030-94583-1_19(378-399)Online publication date: 16-Jan-2022
  • (2019)Design and Multi-Abstraction-Level Evaluation of a NoC Router for Mixed-Criticality Real-Time SystemsACM Journal on Emerging Technologies in Computing Systems10.1145/326481815:1(1-37)Online publication date: 14-Feb-2019
  • (2017)DAS: An Efficient NoC Router for Mixed-Criticality Real-Time Systems2017 IEEE International Conference on Computer Design (ICCD)10.1109/ICCD.2017.42(229-232)Online publication date: Nov-2017

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