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Understanding Performance Differences of FPGAs and GPUs: (Abtract Only)

Published: 15 February 2018 Publication History

Abstract

The notorious power wall has significantly limited the scaling for general-purpose processors. To address this issue, various accelerators, such as GPUs and FPGAs, emerged to achieve better performance and energy-efficiency. Between these two programmable accelerators, a natural question arises: which applications are better suited for FPGAs, which for GPUs, and why?
In this paper, our goal is to better understand the performance differences between FPGAs and GPUs and provide more insights to the community. We intentionally start with a widely used GPU-friendly benchmark suite Rodinia, and port 11 of the benchmarks (15 kernels) onto FPGAs using the more portable and programmable high-level synthesis C. We provide a simple five-step strategy for FPGA accelerator designs that can be easily understood and mastered by software programmers, and present a quantitative performance breakdown of each step. Then we propose a set of performance metrics, including normalized operations per cycle (OPC_norm) for each pipeline, and effective parallel factor (effective_para_factor), to compare the performance of GPU and FPGA accelerator designs. We find that for 6 out of the 15 kernels, today's FPGAs can provide comparable performance or even achieve better performance, while only consume about 1/10 of GPUs' power (both on the same technology node). We observe that FPGAs usually have higher OPC_norm in most kernels in light of their customized deep pipeline but lower effective_para_factor due to far lower memory bandwidth than GPUs. Future FPGAs should increase their off-chip bandwidth and clock frequency to catch up with GPUs.

Cited By

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  • (2024)The Role of Field-Programmable Gate Arrays in the Acceleration of Modern High-Performance Computing WorkloadsComputer10.1109/MC.2024.337838057:7(66-76)Online publication date: Jul-2024
  • (2024)Parallel Computing with GPU: An accelerator for Data-Centric High Performance Computing2024 1st International Conference on Innovative Engineering Sciences and Technological Research (ICIESTR)10.1109/ICIESTR60916.2024.10798202(1-6)Online publication date: 14-May-2024
  • (2023)FPGA-Based CNN for Eye Detection in an Iris Recognition at a Distance SystemElectronics10.3390/electronics1222471312:22(4713)Online publication date: 20-Nov-2023
  • Show More Cited By

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Published In

cover image ACM Conferences
FPGA '18: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
February 2018
310 pages
ISBN:9781450356145
DOI:10.1145/3174243
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 February 2018

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Author Tags

  1. accelerator
  2. fpga
  3. gpu
  4. rodinia

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FPGA '18
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FPGA '18 Paper Acceptance Rate 10 of 116 submissions, 9%;
Overall Acceptance Rate 125 of 627 submissions, 20%

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FPGA '25

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Cited By

View all
  • (2024)The Role of Field-Programmable Gate Arrays in the Acceleration of Modern High-Performance Computing WorkloadsComputer10.1109/MC.2024.337838057:7(66-76)Online publication date: Jul-2024
  • (2024)Parallel Computing with GPU: An accelerator for Data-Centric High Performance Computing2024 1st International Conference on Innovative Engineering Sciences and Technological Research (ICIESTR)10.1109/ICIESTR60916.2024.10798202(1-6)Online publication date: 14-May-2024
  • (2023)FPGA-Based CNN for Eye Detection in an Iris Recognition at a Distance SystemElectronics10.3390/electronics1222471312:22(4713)Online publication date: 20-Nov-2023
  • (2022)Mobile or FPGA? A Comprehensive Evaluation on Energy Efficiency and a Unified Optimization FrameworkACM Transactions on Embedded Computing Systems10.1145/352857821:5(1-22)Online publication date: 9-Dec-2022
  • (2022)Int-Monitor: a model triggered hardware trojan in deep learning acceleratorsThe Journal of Supercomputing10.1007/s11227-022-04759-y79:3(3095-3111)Online publication date: 29-Aug-2022
  • (2021)A Case for Function-as-a-Service with Disaggregated FPGAs2021 IEEE 14th International Conference on Cloud Computing (CLOUD)10.1109/CLOUD53861.2021.00047(333-344)Online publication date: Sep-2021
  • (2020)LLVM-based automation of memory decoupling for OpenCL applications on FPGAsMicroprocessors & Microsystems10.1016/j.micpro.2019.10290972:COnline publication date: 1-Feb-2020
  • (2019)Exploring the Efficiency of OpenCL Pipe for Hiding Memory Latency on Cloud FPGAs2019 IEEE High Performance Extreme Computing Conference (HPEC)10.1109/HPEC.2019.8916236(1-7)Online publication date: Sep-2019
  • (2019)A Fast Parallel K-Modes Algorithm for Clustering Nucleotide Sequences to Predict Translation Initiation SitesJournal of Computational Biology10.1089/cmb.2018.0245Online publication date: 20-Feb-2019
  • (2019)A survey of deep learning techniques for autonomous drivingJournal of Field Robotics10.1002/rob.2191837:3(362-386)Online publication date: 14-Nov-2019

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