Article

Free access

Performance analysis of multiprocessor cache consistency protocols using generalized timed Petri nets

Authors:

Mary K. Vernon,

Mark A. HollidayAuthors Info & Claims

SIGMETRICS '86/PERFORMANCE '86: Proceedings of the 1986 ACM SIGMETRICS joint international conference on Computer performance modelling, measurement and evaluation

Pages 9 - 17

https://doi.org/10.1145/317499.317534

Published: 01 May 1986 Publication History

Abstract

We use an exact analytical technique, based on Generalized Timed Petri Nets (GTPNs), to study the performance of shared bus cache consistency protocols for multiprocessors. We develop a general framework within which the key characteristics of the Write-Once protocol and four enhancements that have been combined in various ways in the literature can be identified and evaluated. We then quantitatively assess the performance gains for each of the four enhancements. We consider three levels of data sharing in our workload models. One of the enhancements substantially improves system performance in all cases. Two enhancements are shown to have negligible effect over the range of workloads analyzed. The fourth enhancement shows a small improvement for low levels of sharing, but shows more substantial improvement as sharing is increased, if we assume a “good access pattern”. The effects of two architectural parameters, the blocksize and the main memory cycle time are also considered.

References

[1]

Ajmone Marsan, M., G. Balbo, and G. Conte, "A Class of Generalized Stochastic Petri Nets", A CM Trans. on Computer Systems, Vol. 2, May 1984, pp. 93-122.

Digital Library

[2]

Archibald, J., and J.-L. Baer, "An Evaluation of Cache Coherence Solutions in Shared-Bus Multiprocessors," Technical Report 85-10-05, Dept. of Comp. Sci., Univ. of Washington, October 1985.

[3]

Dubois, M., and F. A. Briggs, "Effects of Cache Coherency in Multiprocessors', IEEE Trans. on Computers, Vol. C-31, November 1982, pp. 1083-1099.

[4]

S.J. Frank, "Tightly Coupled Multiprocessor System Speeds Memory Access Times," Electronics, Vol. 57, no. 1, January 1984, pp. 164-169.

[5]

Goodman, J.R., "Using Cache Memory to Reduce Processor-Memory Traffic," in Proc. o.f l Oth int. Syrup. on Computer Architecture, June 1983, pp. 124-131.

Digital Library

[6]

Holliday, M. A., and M. K. Vernon, "A Generalized Timed Petri Net Model for Performance Analysis," Proc. int'l. Workshop on Timed Petri Nets, Torino, Italy, July 1985.

Digital Library

[7]

Holliday, M. A., and M. K. Vernon, "Exact Performance Estimates for Multiprocessor Memory and Bus Interference", Technical Report #594, Comp. Sci. Dept., UW-Madison, May 1985.

[8]

Katz, R., S. Eggers, D.A. Wood, C. Perkins, and R.G. Sheldon, "Implementing a Cache Consistency Protocol," Proc. of l#th Int. Syrup. on Computer Architecture, June 1985, pp. 276-283.

Digital Library

[9]

McCreight, E., "The DRAGON Computer System: An Early Overview," NATO Advanced Study Institute on Microarchitecture of VLSI Computer6, Urbino, Italy, July 1984.

[10]

Molioy, M. K., "Performance Analysis Using Stochastic Petri Nets", IEEE Trans. on Computers, Vol. C-31, Sept. 1982, pp. 913-917.

[11]

Molloy, M. K., "Discrete-Time Stochastic Petri Nets", IEEE Trans. on Soft. Engr., Vol. SF_,-11, April 1985, pp. 417-423.

Digital Library

[12]

Natkin, S., "Reseaux de Petri Stochastiques', These de Docteur-lngenieur, CNAM-Paris, June 1980.

[13]

Papamarcos, M., and J. Patel, "A Low Overhead Coherence Solution for Multiprocessors with Private Cache Memories," Proc. of 11th }nt. SiImp. on Compttter Architecture, June 1984, pp. 348-354.

Digital Library

[14]

Rudolph, L., and Z. Segall, "Dynamic Decentralized Cache Schemes for MIMD Parallel Processors," Proc. of llth Int. Sl./mp. on Computer Architecture, June 1984, pp. 340-347.

Digital Library

[15]

Smith, A.J., "Cache Memories," Computing Surveys, Vol. I4, no. 3, pp. 473-530, September 1982.

Digital Library

[16]

Smith, A. J., "Cache Evaluation and the Impact of Workload Choice", Proc. of lRth Int. Syrup. on Computer Architecture, June 1985.

Digital Library

[17]

Smith, A. J., "Line (Block) Size Choice for CPU Cache Memories", Technical Report CSD 85/239, Computer Science Division, Univ. of Calif. at Berkeley, 1985.

Digital Library

Cited By

Tsitsoulis ABourbakis N(2013)Modeling of Multi-Image/Video Flow on a Multiprocessor Surveillance SystemInternational Journal of Monitoring and Surveillance Technologies Research10.4018/ijmstr.20130101011:1(1-15)Online publication date: 1-Jan-2013
https://dl.acm.org/doi/10.4018/ijmstr.2013010101
Lindemann CSchön F(2005)Modeling relaxed memory consistency protocolsQuantitative Evaluation of Computing and Communication Systems10.1007/BFb0024329(385-400)Online publication date: 9-Jun-2005
https://doi.org/10.1007/BFb0024329
Kattner REger MMüller-Schloer C(2005)Modeling cache coherence overhead with geometric objectsParallel Processing: CONPAR 94 — VAPP VI10.1007/3-540-58430-7_39(438-448)Online publication date: 3-Jun-2005
https://doi.org/10.1007/3-540-58430-7_39
Show More Cited By

Index Terms

Performance analysis of multiprocessor cache consistency protocols using generalized timed Petri nets

Recommendations

Performance analysis of multiprocessor cache consistency protocols using generalized timed Petri nets

We use an exact analytical technique, based on Generalized Timed Petri Nets (GTPNs), to study the performance of shared bus cache consistency protocols for multiprocessors. We develop a general framework within which the key characteristics of the Write-...
Multiprocessor cache memory performance: characterization and optimization
Performance analysis of cache coherence protocols in shared-memory multiprocessor systems under generalized access environments

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

SIGMETRICS '86/PERFORMANCE '86: Proceedings of the 1986 ACM SIGMETRICS joint international conference on Computer performance modelling, measurement and evaluation

May 1986

262 pages

ISBN:0897911849

DOI:10.1145/317499

Chairmen:
Harry G. Perros
North Carolina State Univ., Raleigh
,
William J. Stewart
North Carolina State Univ., Raleigh
,
Kishor S. Trivedi

ACM SIGMETRICS Performance Evaluation Review Volume 14, Issue 1
May 1986
277 pages
ISSN:0163-5999
DOI:10.1145/317531
Editor:
Blaine D. Galther
Burroghs Corp., Santa Ana, CA
Issue’s Table of Contents

Copyright © 1986 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGMETRICS: ACM Special Interest Group on Measurement and Evaluation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1986

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

SIGMETRICS86

Sponsor:

SIGMETRICS

SIGMETRICS86: Joint International Conference on Measurement and Modeling of Computer Systems

North Carolina, Raleigh, USA

Acceptance Rates

Overall Acceptance Rate 459 of 2,691 submissions, 17%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

30
Total Citations
View Citations
444
Total Downloads

Downloads (Last 12 months)62
Downloads (Last 6 weeks)13

Reflects downloads up to 15 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Tsitsoulis ABourbakis N(2013)Modeling of Multi-Image/Video Flow on a Multiprocessor Surveillance SystemInternational Journal of Monitoring and Surveillance Technologies Research10.4018/ijmstr.20130101011:1(1-15)Online publication date: 1-Jan-2013
https://dl.acm.org/doi/10.4018/ijmstr.2013010101
Lindemann CSchön F(2005)Modeling relaxed memory consistency protocolsQuantitative Evaluation of Computing and Communication Systems10.1007/BFb0024329(385-400)Online publication date: 9-Jun-2005
https://doi.org/10.1007/BFb0024329
Kattner REger MMüller-Schloer C(2005)Modeling cache coherence overhead with geometric objectsParallel Processing: CONPAR 94 — VAPP VI10.1007/3-540-58430-7_39(438-448)Online publication date: 3-Jun-2005
https://doi.org/10.1007/3-540-58430-7_39
Westall JGeist R(1997)A hybrid tool for the performance evaluation of NUMA architecturesProceedings of the 29th conference on Winter simulation10.1145/268437.268736(1029-1036)Online publication date: 1-Dec-1997
https://dl.acm.org/doi/10.1145/268437.268736
Geist RWestall J(1996)Performance and availability evaluation of NUMA architecturesProceedings of IEEE International Computer Performance and Dependability Symposium10.1109/IPDS.1996.540228(271-280)Online publication date: 1996
https://doi.org/10.1109/IPDS.1996.540228
Tomasevic MMilutinovic V(1994)Hardware Approaches to Cache Coherence in Shared-Memory Multiprocessors Part 2IEEE Micro10.1109/40.33139214:6(61-66)Online publication date: 1-Dec-1994
https://dl.acm.org/doi/10.1109/40.331392
Tomasevic MMilutinovic V(1993)A survey of hardware solutions for maintenance of cache coherence in shared memory multiprocessors[1993] Proceedings of the Twenty-sixth Hawaii International Conference on System Sciences10.1109/HICSS.1993.270604(863-872)Online publication date: 1993
https://doi.org/10.1109/HICSS.1993.270604
Nanda AJiang H(1992)Analysis of directory based cache coherence schemes with multistage networksProceedings of the 1992 ACM annual conference on Communications10.1145/131214.131276(485-492)Online publication date: 1-Apr-1992
https://dl.acm.org/doi/10.1145/131214.131276
Tsuei TVernon M(1992)A Multiprocessor Bus Design Model Validated by System MeasurementIEEE Transactions on Parallel and Distributed Systems10.1109/71.1806263:6(712-727)Online publication date: 1-Nov-1992
https://dl.acm.org/doi/10.1109/71.180626
Chiang MSohi G(1992)Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented EnvironmentIEEE Transactions on Computers10.1109/12.12744241:3(297-317)Online publication date: 1-Mar-1992
https://dl.acm.org/doi/10.1109/12.127442
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents