Interconnect Physical Optimization

The SoC Interconnect is one of the most important IPs in modern chips as it is the logical and physical instantiation of an SoC architecture and carries virtually all the SoC data. Interconnect IPs have to carry non-coherent, cache coherent, subsystem and service traffic. Another unique characteristic of SoC interconnect IP is that it changes many times per project and is unique for each project. Hence, the interconnect IP is the most configurable of all major IPs in a chip. The current state of the art in interconnect is the Network on Chip (NoC) distinguished by use of packetized transport and distributed arbitration. This interconnect IP approach is proven in billions of shipping SoCs. However, the world is changing. With the 16nm processes (and below), timing closure has become a major issue as there are valid logical architectures that are not timing closable in the place and route phase of the design. This has made it necessary to consider physical layout effects in the design of interconnect IPs at the architecture and RTL logic phases of chip development. Providing a timing-verified interconnect IP to the place and route group has become a new silicon success requirement. Interconnect Physical Optimization links the logic and physical design realms, providing a more optimal starting point for the place and route process to minimize the number of place and route iteration cycles. This paper will discuss an interconnect physical optimization capability, called PIANO, which addresses automation of the timing closure process in order to accelerate design of interconnect IPs and reduce the need to over-engineer the interconnect. The paper will also cover the inputs needed to make PIANO produce optimal results and outputs which enable optimization of latency-sensitive SoC connections.