research-article

Combining PREM compilation and ILP scheduling for high-performance and predictable MPSoC execution

Authors:

Björn Forsberg,

Zdeněk Hanzálek,

Andrea MarongiuAuthors Info & Claims

PMAM'18: Proceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores

Pages 11 - 20

https://doi.org/10.1145/3178442.3178444

Published: 24 February 2018 Publication History

Abstract

Many applications require both high performance and predictable timing. High-performance can be provided by COTS Multi-Core System on Chips (MPSoC), however, as cores in these systems share the memory bandwidth they are susceptible to interference from each other, which is a problem for timing predictability. We achieve predictability on multi-cores by employing the predictable execution model (PREM), which splits execution into a sequence of memory and compute phases, and schedules these such that only a single core is executing a memory phase at a time.

We present a toolchain consisting of a compiler and an Integer Linear Programming scheduling model. Our compiler uses loop analysis and tiling to transform application code into PREM compliant binaries. Furthermore, we solve the problem of scheduling execution on multiple cores while preventing interference of memory phases.

We evaluate our toolchain on Advanced-Driver-Assistance-Systems-like scenario containing matrix multiplications and FFT computations on NVIDIA TX1. The results show that our approach maintains similar average performance and improves variance of completion times by a factor of 9.

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Cited By

Dudzik KKirschner MBetancourt VBecker J(2024)Work in Progress: Predictable Execution of Isolated Real-Time Tasks on Multicore Systems Using the LET Paradigm2024 IEEE 30th Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS61025.2024.00038(386-389)Online publication date: 13-May-2024
https://doi.org/10.1109/RTAS61025.2024.00038
Thilakasiri TBecker M(2023)Methods to Realize Preemption in Phased Execution ModelsACM Transactions on Embedded Computing Systems10.1145/360913222:5s(1-25)Online publication date: 31-Oct-2023
https://dl.acm.org/doi/10.1145/3609132
Capodieci NBurgio PCavicchioli ROlmedo ISolieri MBertogna M(2022)Real-Time Requirements for ADAS Platforms Featuring Shared Memory HierarchiesIEEE Design & Test10.1109/MDAT.2020.301382839:1(35-41)Online publication date: Feb-2022
https://doi.org/10.1109/MDAT.2020.3013828
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Index Terms

Combining PREM compilation and ILP scheduling for high-performance and predictable MPSoC execution
1. Computer systems organization
  1. Real-time systems
    1. Real-time system architecture
2. Software and its engineering
  1. Software notations and tools
    1. Compilers
  2. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Process management
        Scheduling

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Published In

cover image ACM Conferences

PMAM'18: Proceedings of the 9th International Workshop on Programming Models and Applications for Multicores and Manycores

February 2018

89 pages

ISBN:9781450356459

DOI:10.1145/3178442

Editors:
Quan Chen
Shanghai Jiao Tong University, China
,
Zhiyi Huang
University of Otago, New Zealand
,
Pavan Balaji
Argonne National Laboratory, USA

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 24 February 2018

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Research-article
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Refereed limited

Funding Sources

Horizon 2020 Framework Programme

Conference

PPoPP '18

Sponsor:

PPoPP '18: 23nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming

February 24 - 28, 2018

Vienna, Austria

Acceptance Rates

PMAM'18 Paper Acceptance Rate 9 of 17 submissions, 53%;

Overall Acceptance Rate 53 of 97 submissions, 55%

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Cited By

Dudzik KKirschner MBetancourt VBecker J(2024)Work in Progress: Predictable Execution of Isolated Real-Time Tasks on Multicore Systems Using the LET Paradigm2024 IEEE 30th Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS61025.2024.00038(386-389)Online publication date: 13-May-2024
https://doi.org/10.1109/RTAS61025.2024.00038
Thilakasiri TBecker M(2023)Methods to Realize Preemption in Phased Execution ModelsACM Transactions on Embedded Computing Systems10.1145/360913222:5s(1-25)Online publication date: 31-Oct-2023
https://dl.acm.org/doi/10.1145/3609132
Capodieci NBurgio PCavicchioli ROlmedo ISolieri MBertogna M(2022)Real-Time Requirements for ADAS Platforms Featuring Shared Memory HierarchiesIEEE Design & Test10.1109/MDAT.2020.301382839:1(35-41)Online publication date: Feb-2022
https://doi.org/10.1109/MDAT.2020.3013828
Park SLee JKim H(2022)Software-Level Memory Regulation to Reduce Execution Time Variation on Multicore Real-Time SystemsIEEE Access10.1109/ACCESS.2022.320370210(93799-93811)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3203702
Lugo TLozano SFernandez JCarretero J(2022)A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore PlatformsIEEE Access10.1109/ACCESS.2022.315189110(21853-21882)Online publication date: 2022
https://doi.org/10.1109/ACCESS.2022.3151891
Matějka JForsberg BSojka MŠůcha PBenini LMarongiu AHanzálek Z(2022)Combining PREM compilation and static scheduling for high-performance and predictable MPSoC executionParallel Computing10.1016/j.parco.2018.11.00285:C(27-44)Online publication date: 20-Apr-2022
https://dl.acm.org/doi/10.1016/j.parco.2018.11.002
Reder SBecker J(2020)WCET-aware Code Generation and Communication Optimization for Parallelizing Compilers2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116400(210-215)Online publication date: Mar-2020
https://doi.org/10.23919/DATE48585.2020.9116400
Soliman MGracioli GTabish RPellizzoni RCaccamo M(2019)Segment Streaming for the Three-Phase Execution Model: Design and Implementation2019 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS46320.2019.00032(260-273)Online publication date: Dec-2019
https://doi.org/10.1109/RTSS46320.2019.00032
Fort FForget J(2019)Code generation for multi-phase tasks on a multi-core distributed memory platform2019 IEEE 25th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)10.1109/RTCSA.2019.8864558(1-6)Online publication date: Aug-2019
https://doi.org/10.1109/RTCSA.2019.8864558

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