research-article

Resilient AES Against Side-Channel Attack Using All-Spin Logic

Authors:

Qutaiba Alasad,

Jie LinAuthors Info & Claims

GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSI

Pages 57 - 62

https://doi.org/10.1145/3194554.3194595

Published: 30 May 2018 Publication History

Abstract

The new generation of spintronic devices, Hybrid Spintronic-CMOS devices including Magnetic Tunnel Junction (MTJ), have been utilized to overcome Moore's law limitation as well as preserve higher performance with lower cost. However, implementing these devices as a hardware cryptosystem is vulnerable to side channel attacks (SCAs) due to the differential power at the output of the Hybrid Spintronic-CMOS device and asymmetric read/write operations in MTJ. One of the most severe SCAs is the power analysis attack (PAA), in which an attacker can observe the output current of the device and extract the secret key. In this paper, we employ the All Spin Logic Device (ASLD) to implement protected AES cryptography for the first time. More precisely, we realize that in additional to ASLD features, such as small area, non-volatile memory, high density and low operating voltage, this device has another unique feature: identical power dissipation through the switching operations. Such properties can be effectively leveraged to prevent SCA.

References

[1]

X. Li, C. Yang, J. Ma, Y. Liu, and S. Yin, "Energy-efficient side-channel attack countermeasure with awareness and hybrid configuration based on it," IEEE Transactions on VLSI Systems, 2017.

[2]

P. Kocher, "Design and validation strategies for obtaining assurance in countermeasures to power analysis and related," in in Attacks, in the proceedings of the NIST Physical Security Workshop, 2005.

[3]

A. Jaiswal, I. Chakraborty, and K. Roy, "Energy-efficient memory using magnetoelectric switching of ferromagnets," IEEE Magnetics Letters, vol. 8, pp. 1--5, 2017.

[4]

Y. Wang, L. Ni, C. H. Chang, and H. Yu, "Dw-aes: A domain-wall nanowire-based aes for high throughput and energy-efficient data encryption in non-volatile memory," IEEE Transactions on Information Forensics and Security, 2016.

Digital Library

[5]

K. J. Smith, "Methodologies for power analysis attacks on hardware implementations of aes," Thesis. Rochester Institute of Technology., 2009.

[6]

F. Zhang and Z. J. Shi, "Differential and correlation power analysis attacks on hmac-whirlpool," in 2011 8th ITNG, 2011.

Digital Library

[7]

K. Tiri et al., "A dynamic and differential cmos logic with signal independent power consumption to withstand differential power analysis on smart cards," in Solid-State Circuits Conference, 2002.

[8]

M. Khan et al., "Side-channel attack on sttram based cache for cryptographic application," in IEEE International Conference on Computer Design (ICCD), 2017.

[9]

A. Moradi et al., Pushing the Limits: A Very Compact and a Threshold Implementation of AES. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011.

[10]

P. Liu et al., "A low overhead dpa countermeasure circuit based on ring oscillators," IEEE Transactions on Circuits and Systems II: Express Briefs, 2010.

Digital Library

[11]

Q. Alasad, J.-S. Yuan, and Y. Bi, "Logic locking using hybrid cmos and emerging sinw fets," Electronics, vol. 6, 2017.

[12]

Q. Alasad and J. Yuan, "Logic obfuscation against ic reverse engineering attacks using plgs," in IEEE International Conference on Computer Design (ICCD), 2017.

[13]

Q. Alasad, J. Yuan, and D. Fan, "Leveraging all-spin logic to improve hardware security," in Proceedings of the on GLSVLSI '17, 2017.

Digital Library

[14]

H. Dery, P. Dalal, L. Cywinski, and L. J. Sham, "Spin-based logic in semiconductors for reconfigurable large-scale circuits," Nature, 2007.

[15]

B. Behin-Aein, D. Datta, S. Salahuddin, and S. Datta, "Proposal for an all-spin logic device with built-in memory," Nature, vol. 5, 2010.

[16]

K. Y. Camsari, S. Ganguly, and S. Datta, "Modular approach to spintronics," in 2015 Scientific Reports, vol. 5.

[17]

Z. Pajouhi et al., "Exploring spin-transfer-torque devices for logic applications," IEEE Transactions on CAD, 2015.

Digital Library

[18]

V. Rijmen et al., "Advanced encryption standard," Proceedings of Federal Information Processing Standards Publications, NIST, 2001.

[19]

J. M. Renders et al., "Hybridizing genetic algorithms with hill-climbing methods for global optimization: two possible ways," in IEEE Proceedings on EC, 1994.

[20]

M. G. Mankalale and S. S. Sapatnekar, "Optimized standard cells for all-spin logic," J. Emerg. Technol. Comput. Syst., vol. 13, no. 2, pp. 21:1--21:22, Nov. 2016.

Digital Library

[21]

K. Malbrain, "Byte-oriented-aes: A public domain byteoriented implementation of aes in c," Available: " https://code.google.com/p/byte-oriented-aes/", 2009.

[22]

S. Mathew et al., "340mV--1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(24)2 polynomials in 22nm tri-gate cmos," in Symposium on VLSI Circuits Digest of Technical Papers, 2014.

[23]

Z. Abid et al., "Efficient cmol gate designs for cryptography applications," IEEE Transactions on Nanotechnology, 2009.

Digital Library

[24]

Q. Tian and S. A. Huss, "Power amount analysis: Another way to understand power traces in side channel attacks," in 2nd ICDIPC, July 2012.

Cited By

Selvam RTyagi A(2023)Residue Number System (RNS) and Power Distribution Network Topology-Based Mitigation of Power Side-Channel AttacksCryptography10.3390/cryptography80100018:1(1)Online publication date: 21-Dec-2023
https://doi.org/10.3390/cryptography8010001
Kumar SChatterjee SDabhi CAmrouch HSingh Chauhan Y(2022)A Novel Approach to Mitigate Power Side-Channel Attacks for Emerging Negative Capacitance Transistor Technology2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)10.1109/NEWCAS52662.2022.9842186(504-508)Online publication date: 19-Jun-2022
https://doi.org/10.1109/NEWCAS52662.2022.9842186
Poudel BMunir AKong JKhan M(2021)Design and Validation of Low-Power Secure and Dependable Elliptic Curve CryptosystemJournal of Low Power Electronics and Applications10.3390/jlpea1104004311:4(43)Online publication date: 12-Nov-2021
https://doi.org/10.3390/jlpea11040043
Show More Cited By

Index Terms

Resilient AES Against Side-Channel Attack Using All-Spin Logic
1. Security and privacy
  1. Security in hardware
    1. Hardware attacks and countermeasures

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Published In

cover image ACM Conferences

GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSI

May 2018

533 pages

ISBN:9781450357241

DOI:10.1145/3194554

General Chair:
Deming Chen
University of Illinois, USA
,
Program Chairs:
Houman Homayoun
George Mason University, USA
,
Baris Taskin
Drexel University, USA

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 30 May 2018

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GLSVLSI '18

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GLSVLSI '18: Great Lakes Symposium on VLSI 2018

May 23 - 25, 2018

IL, Chicago, USA

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GLSVLSI '18 Paper Acceptance Rate 48 of 197 submissions, 24%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Selvam RTyagi A(2023)Residue Number System (RNS) and Power Distribution Network Topology-Based Mitigation of Power Side-Channel AttacksCryptography10.3390/cryptography80100018:1(1)Online publication date: 21-Dec-2023
https://doi.org/10.3390/cryptography8010001
Kumar SChatterjee SDabhi CAmrouch HSingh Chauhan Y(2022)A Novel Approach to Mitigate Power Side-Channel Attacks for Emerging Negative Capacitance Transistor Technology2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)10.1109/NEWCAS52662.2022.9842186(504-508)Online publication date: 19-Jun-2022
https://doi.org/10.1109/NEWCAS52662.2022.9842186
Poudel BMunir AKong JKhan M(2021)Design and Validation of Low-Power Secure and Dependable Elliptic Curve CryptosystemJournal of Low Power Electronics and Applications10.3390/jlpea1104004311:4(43)Online publication date: 12-Nov-2021
https://doi.org/10.3390/jlpea11040043
Alasad QLin JYuan JFan DAwad A(2021)Resilient and Secure Hardware Devices Using ASLACM Journal on Emerging Technologies in Computing Systems10.1145/342998217:2(1-26)Online publication date: 6-Jan-2021
https://dl.acm.org/doi/10.1145/3429982
Zheng SLiu XZang SDeng YHuang DOu C(2021)A Persistent Fault-Based Collision Analysis Against the Advanced Encryption StandardIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.304968740:6(1117-1129)Online publication date: Jun-2021
https://doi.org/10.1109/TCAD.2021.3049687
Knechtel JPatnaik SNabeel MAshraf MChauhan YHenkel JSinanoglu OAmrouch H(2020)Power Side-Channel Attacks in Negative Capacitance TransistorIEEE Micro10.1109/MM.2020.300588340:6(74-84)Online publication date: 1-Nov-2020
https://doi.org/10.1109/MM.2020.3005883
Ferdaus FRahman M(2020)Security of Emerging Memory ChipsEmerging Topics in Hardware Security10.1007/978-3-030-64448-2_14(357-390)Online publication date: 10-Nov-2020
https://doi.org/10.1007/978-3-030-64448-2_14
Rangarajan NPatnaik SKnechtel JRakheja SSinanoglu ORangarajan NPatnaik SKnechtel JRakheja SSinanoglu O(2012)Resilience Against Side-Channel Attacks in Emerging TechnologiesThe Next Era in Hardware Security10.1007/978-3-030-85792-9_8(211-248)Online publication date: 24-Feb-2012
https://doi.org/10.1007/978-3-030-85792-9_8
Rangarajan NPatnaik SKnechtel JRakheja SSinanoglu ORangarajan NPatnaik SKnechtel JRakheja SSinanoglu O(2012)IntroductionThe Next Era in Hardware Security10.1007/978-3-030-85792-9_1(1-34)Online publication date: 24-Feb-2012
https://doi.org/10.1007/978-3-030-85792-9_1

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