Session details: Synthesis & verification
Session Chair: 
Josh BerdineAuthors Info & Claims
Josh BerdineAuthors Info & ClaimsAbstract
No abstract available.
Index Terms
- Session details: Synthesis & verification
Index terms have been assigned to the content through auto-classification.
Recommendations
Hand-in-hand verification of high-level synthesis
GLSVLSI '07: Proceedings of the 17th ACM Great Lakes symposium on VLSIThis paper describes a formal verification methodology of high-level synthesis (HLS) process. The abstraction level of the input to HLS is so high compared to thatof the output that the verification has to proceed hand-in-hand with the synthesis ...
Comments
Information & Contributors
Information
Published In
Copyright © 2013 Copyright is held by the owner/author(s).
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 23 January 2013
Published in SIGPLAN Volume 48, Issue 1
Check for updates
Qualifiers
- Section
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Reflects downloads up to 15 Oct 2024
Other Metrics
Citations
View Options
Get Access
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in