research-article

Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints

Authors:

Francisco J. H. Santiago,

Mohammad Saeed Ansari,

Bruce F. Cockburn,

Fabrizio Lombardi,

Jie HanAuthors Info & Claims

GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSI

Pages 393 - 398

https://doi.org/10.1145/3299874.3319454

Published: 13 May 2019 Publication History

Abstract

Taking advantage of the error resilience in many applications as well as the perceptual limitations of humans, numerous approximate arithmetic circuits have been proposed that trade off accuracy for higher speed or lower power in emerging applications that exploit approximate computing. However, characterizing the various approximate designs for a specific application under certain performance constraints becomes a new challenge. In this paper, approximate adders and multipliers are evaluated and compared for a better understanding of their characteristics when the implementations are optimized for performance or power. Although simple truncation can effectively reduce the hardware of an arithmetic circuit, it is shown that some other designs perform better in speed, power and power-delay product. For instance, many approximate adders have a higher performance than a truncated adder. A truncated multiplier is faster but consumes a higher power than most approximate designs for achieving a similar mean error magnitude. The logarithmic multipliers are very fast and power-efficient at a lower accuracy. Approximate multipliers can also be generated by an automated process to be very efficient while ensuring a sufficiently high accuracy.

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Cited By

Arunachalam AKundu SRaha ABanerjee SNatarajan SBasu K(2023)A Novel Low-Power Compression Scheme for Systolic Array-Based Deep Learning AcceleratorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319803642:4(1085-1098)Online publication date: 1-Apr-2023
https://dl.acm.org/doi/10.1109/TCAD.2022.3198036
Najafi ANajafi AMüller JYu WGarcia-Ortiz A(2023)Approximate Computing in Critical Applications: ECG Arrhythmia Classification2023 12th International Conference on Modern Circuits and Systems Technologies (MOCAST)10.1109/MOCAST57943.2023.10176813(1-4)Online publication date: 28-Jun-2023
https://doi.org/10.1109/MOCAST57943.2023.10176813
Sathish KJagadeesh P(2023)An Efficient Design and Performance Analysis of Novel 8 Bit Modified Wallace Multiplier Using Sklansky Adder in Comparison with Kogge-Stone Adder (KSA)2023 Eighth International Conference on Science Technology Engineering and Mathematics (ICONSTEM)10.1109/ICONSTEM56934.2023.10142607(1-7)Online publication date: 6-Apr-2023
https://doi.org/10.1109/ICONSTEM56934.2023.10142607
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Index Terms

Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints
1. General and reference
  1. Cross-computing tools and techniques
    1. Evaluation
    2. Measurement
  2. Document types
    1. Surveys and overviews
2. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Arithmetic and datapath circuits
      2. Combinational circuits

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cover image ACM Conferences

GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSI

May 2019

562 pages

ISBN:9781450362528

DOI:10.1145/3299874

General Chairs:
Houman Homayoun
George Mason University, USA
,
Baris Taskin
Drexel University, USA
,
Program Chairs:
Tinoosh Mohsenin
UMBC, USA
,
Weisheng Zhao
Beihang University, China

Copyright © 2019 ACM.

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SIGDA: ACM Special Interest Group on Design Automation

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Association for Computing Machinery

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Publication History

Published: 13 May 2019

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Natural Sciences and Engineering Research Council of Canada (NSERC)

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GLSVLSI '19

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SIGDA

GLSVLSI '19: Great Lakes Symposium on VLSI 2019

May 9 - 11, 2019

VA, Tysons Corner, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Arunachalam AKundu SRaha ABanerjee SNatarajan SBasu K(2023)A Novel Low-Power Compression Scheme for Systolic Array-Based Deep Learning AcceleratorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319803642:4(1085-1098)Online publication date: 1-Apr-2023
https://dl.acm.org/doi/10.1109/TCAD.2022.3198036
Najafi ANajafi AMüller JYu WGarcia-Ortiz A(2023)Approximate Computing in Critical Applications: ECG Arrhythmia Classification2023 12th International Conference on Modern Circuits and Systems Technologies (MOCAST)10.1109/MOCAST57943.2023.10176813(1-4)Online publication date: 28-Jun-2023
https://doi.org/10.1109/MOCAST57943.2023.10176813
Sathish KJagadeesh P(2023)An Efficient Design and Performance Analysis of Novel 8 Bit Modified Wallace Multiplier Using Sklansky Adder in Comparison with Kogge-Stone Adder (KSA)2023 Eighth International Conference on Science Technology Engineering and Mathematics (ICONSTEM)10.1109/ICONSTEM56934.2023.10142607(1-7)Online publication date: 6-Apr-2023
https://doi.org/10.1109/ICONSTEM56934.2023.10142607
Ansari MCockburn BHan J(2022)Low-Power Approximate Logarithmic Squaring Circuit Design for DSP ApplicationsIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2020.298969910:1(500-506)Online publication date: 1-Jan-2022
https://doi.org/10.1109/TETC.2020.2989699
Santiago FJiang HAmrouch HGerstlauer ALiu LHan J(2022)Characterizing Approximate Adders and Multipliers for Mitigating Aging and Temperature DegradationsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.319392869:11(4558-4571)Online publication date: Nov-2022
https://doi.org/10.1109/TCSI.2022.3193928
Pathak KDarji ASarvaiya JBhatt ZGangadwala ADiwan SPatel A(2022)Design of Error-Tolerant and Low-Power Approximate Full AdderMicroelectronics, Communication Systems, Machine Learning and Internet of Things10.1007/978-981-19-1906-0_5(53-66)Online publication date: 12-Jul-2022
https://doi.org/10.1007/978-981-19-1906-0_5
Ansari MCockburn BHan J(2021)An Improved Logarithmic Multiplier for Energy-Efficient Neural ComputingIEEE Transactions on Computers10.1109/TC.2020.299211370:4(614-625)Online publication date: 1-Apr-2021
https://doi.org/10.1109/TC.2020.2992113
Arunachalam AKundu SRaha ABanerjee SNatarajan SBasu K(2021)HardCompress: A Novel Hardware-based Low-power Compression Scheme for DNN Accelerators2021 22nd International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED51717.2021.9424301(457-462)Online publication date: 7-Apr-2021
https://doi.org/10.1109/ISQED51717.2021.9424301
Ansari MGandhi SCockburn BHan J(2021)Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computingIET Computers & Digital Techniques10.1049/cdt2.1201915:4(241-250)Online publication date: 22-Mar-2021
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Towhidy AOmidi RMohammadi K(2021)On the design of radix-K approximate multiplier using 2D pseudo-booth encodingAEU - International Journal of Electronics and Communications10.1016/j.aeue.2021.153988142(153988)Online publication date: Dec-2021
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