research-article

Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints

Authors:

Nikolay Ryzhenko,

Mikhail TalalayAuthors Info & Claims

ISPD '19: Proceedings of the 2019 International Symposium on Physical Design

Pages 41 - 47

https://doi.org/10.1145/3299902.3309744

Published: 04 April 2019 Publication History

Abstract

In this paper, we propose a routing flow for nets within a standard cell that generates layout of standard cells without any design rule violations. Design rules, density rules for metal fill, and pin-access requirements are modeled via Boolean formulas for discrete layout objects on grids. Formulas are translated into a single Boolean satisfiability problem (SAT). Having constraints on net connectivity and candidate routes, the SAT solver produces legal and complete routing concurrently for all nets satisfying mandatory pin-access and density requirements. A SAT-based optimization engine minimizes undesired layout patterns such as DFM (design-for-manufacturing) hot spots.

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A. Sorokin, N. Ryzhenko, SAT-Based Placement Adjustment of FinFETs inside Unroutable Standard Cells Targeting Feasible DRC-Clean Routing, In Proceedings of the 29th ACM Great Lakes Symposium on VLSI (GLSVLSI'19), May 9-11, Washington, D.C., USA.

Cited By

Chen HHsiao CChao WHsieh I(2023)On Generating Cell Library in Advanced Nodes: Efforts and Challenges2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT)10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134126(1-4)Online publication date: 17-Apr-2023
https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134126
Cheng CKahng AKim HKim MLee DPark DWoo M(2022)PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced NodesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309301541:5(1495-1508)Online publication date: May-2022
https://doi.org/10.1109/TCAD.2021.3093015
Cheng CHo CLee DLin BPark D(2021)Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMTIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.306563929:6(1178-1191)Online publication date: Jun-2021
https://doi.org/10.1109/TVLSI.2021.3065639
Show More Cited By

Index Terms

Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Physical synthesis
  2. Very large scale integration design
    1. Standard cell libraries

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cover image ACM Conferences

ISPD '19: Proceedings of the 2019 International Symposium on Physical Design

April 2019

164 pages

ISBN:9781450362535

DOI:10.1145/3299902

General Chair:
Ismail Bustany
Xilinx Inc.
,
Program Chair:
William Swartz
TimberWolf Systems Inc. & University of Texas at Dallas

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation

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New York, NY, United States

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Published: 04 April 2019

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ISPD '19: International Symposium on Physical Design

April 14 - 17, 2019

CA, San Francisco, USA

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ISPD '19 Paper Acceptance Rate 12 of 25 submissions, 48%;

Overall Acceptance Rate 62 of 172 submissions, 36%

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March 16 - 19, 2025

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Cited By

Chen HHsiao CChao WHsieh I(2023)On Generating Cell Library in Advanced Nodes: Efforts and Challenges2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT)10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134126(1-4)Online publication date: 17-Apr-2023
https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134126
Cheng CKahng AKim HKim MLee DPark DWoo M(2022)PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced NodesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309301541:5(1495-1508)Online publication date: May-2022
https://doi.org/10.1109/TCAD.2021.3093015
Cheng CHo CLee DLin BPark D(2021)Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMTIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2021.306563929:6(1178-1191)Online publication date: Jun-2021
https://doi.org/10.1109/TVLSI.2021.3065639
Lee DPark DHo CKang IKim HGao SLin BCheng C(2021)SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced NodesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.303788540:10(2142-2155)Online publication date: Oct-2021
https://doi.org/10.1109/TCAD.2020.3037885
Lee DHo CKang IGao SLin BCheng C(2021)Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology NodesIEEE Journal on Exploratory Solid-State Computational Devices and Circuits10.1109/JXCDC.2021.30890957:1(52-60)Online publication date: Jun-2021
https://doi.org/10.1109/JXCDC.2021.3089095
Park DLee DKang IHoltz CGao SLin BCheng C(2020)Grid-based Framework for Routability Analysis and Diagnosis with Conditional Design RulesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.2977066(1-1)Online publication date: 2020
https://doi.org/10.1109/TCAD.2020.2977066
Sorokin ARyzhenko NHomayoun HTaskin BMohsenin TZhao W(2019)SAT-Based Placement Adjustment of FinFETs inside Unroutable Standard Cells Targeting Feasible DRC-Clean RoutingProceedings of the 2019 Great Lakes Symposium on VLSI10.1145/3299874.3317965(159-164)Online publication date: 13-May-2019
https://dl.acm.org/doi/10.1145/3299874.3317965

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