research-article

CMOS analog four-quadrant multiplier free of voltage reference generators

Authors:

Antonio José Sobrinho de Sousa,

Fabian de Andrade,

Hildeloi dos Santos,

Gabriele Gonçalves,

Maicon Deivid Pereira,

Edson Santana,

Ana Isabela CunhaAuthors Info & Claims

SBCCI '19: Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design

Article No.: 27, Pages 1 - 6

https://doi.org/10.1145/3338852.3339870

Published: 26 August 2019 Publication History

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Abstract

This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. The circuit has voltage-mode inputs and a current-mode output and includes a signal application method that avoids voltage or current reference generators. Simulations have been accomplished for a CMOS 130 nm technology, featuring ±50 mV input voltage range, 60 μW static power and -25 dB maximum THD. The active area is 346 μm².

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Cited By

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Popa C(2024)CMOS Computational Structures Using a Nonlinear Multifunctional Core2024 31st International Conference on Mixed Design of Integrated Circuits and System (MIXDES)10.23919/MIXDES62605.2024.10613987(80-85)Online publication date: 27-Jun-2024
https://doi.org/10.23919/MIXDES62605.2024.10613987
Mahmoodi AAbrishamifar A(2024)A class AB ultra-low-power asymmetrical structured current multiplierAEU - International Journal of Electronics and Communications10.1016/j.aeue.2024.155470(155470)Online publication date: Aug-2024
https://doi.org/10.1016/j.aeue.2024.155470
Popa C(2022)CMOS Analog Building Blocks Using Nonlinear Circuit Core2022 International Conference on Microelectronics (ICM)10.1109/ICM56065.2022.10005451(62-65)Online publication date: 4-Dec-2022
https://doi.org/10.1109/ICM56065.2022.10005451

Index Terms

CMOS analog four-quadrant multiplier free of voltage reference generators
1. Hardware
  1. Integrated circuits

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Information & Contributors

Information

Published In

SBCCI '19: Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design

August 2019

204 pages

ISBN:9781450368445

DOI:10.1145/3338852

General Chair:
João Martino
USP, Brazil
,
Program Chairs:
Marcelo Lubaszewski
UFRGS, Brazil
,
Matteo Reorda
Politec. di Torino, Italy

© 2019 Association for Computing Machinery. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of a national government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 26 August 2019

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Research-article

Funding Sources

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior
Conselho Nacional de Desenvolvimento Científico e Tecnológico

Conference

SBCCI '19

Sponsor:

SIGDA

SBCCI '19: 32nd Symposium on Integrated Circuits and Systems Design

August 26 - 30, 2019

São Paulo, Brazil

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Overall Acceptance Rate 133 of 347 submissions, 38%

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Cited By

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Popa C(2024)CMOS Computational Structures Using a Nonlinear Multifunctional Core2024 31st International Conference on Mixed Design of Integrated Circuits and System (MIXDES)10.23919/MIXDES62605.2024.10613987(80-85)Online publication date: 27-Jun-2024
https://doi.org/10.23919/MIXDES62605.2024.10613987
Mahmoodi AAbrishamifar A(2024)A class AB ultra-low-power asymmetrical structured current multiplierAEU - International Journal of Electronics and Communications10.1016/j.aeue.2024.155470(155470)Online publication date: Aug-2024
https://doi.org/10.1016/j.aeue.2024.155470
Popa C(2022)CMOS Analog Building Blocks Using Nonlinear Circuit Core2022 International Conference on Microelectronics (ICM)10.1109/ICM56065.2022.10005451(62-65)Online publication date: 4-Dec-2022
https://doi.org/10.1109/ICM56065.2022.10005451

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Low power FGMOS-based four-quadrant current multiplier circuits

Gate and Bulk-Driven Four-Quadrant CMOS Analog Multiplier

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