Faster Carry Bit Computation for Adder Circuits with Prescribed Arrival Times

We consider the fundamental problem of constructing fast circuits for the carry bit computation in binary addition. Up to a small additive constant, the carry bit computation reduces to computing an And-Or path, i.e., a formula of type t₀ ∧ (t₁ ∨ (t₂ ∧ (… t_m−1) …) or t₀ ∨ (t₁ ∧ (t₂ ∨ (… t_m−1) …). We present an algorithm that computes the fastest known Boolean circuit for an And-Or path  with given arrival times a(t₀), …, a(t_m−1) for the input signals. Our objective function is delay, a natural generalization of depth with respect to arrival times. The maximum delay of the circuit we compute is log₂ W + log₂ log₂m + log₂ log₂ log₂ m + 4.3, where W := ∑_{i = 0}^m−1 2^a(t_i). Note that ⌈ log₂ W ⌉ is a lower bound on the delay of any circuit depending on inputs t₀, …, t_m−1 with prescribed arrival times. Our method yields the fastest circuits for And-Or paths, carry bit computation, and adders in terms of delay known so far.