Boosting superpage utilization with the shadow memory and the partial-subblock TLB

While superpage is an efficient solution to increase TLB reach, its limited flexibility for address mapping is still a hard issue. Our proposed mechanism has been developed for taking advantage of two previous approaches which resolve the issue partially: the partial-subblock TLB and the shadow memory. Through integration of them, our mechanism enjoys various benefits inherited from the both sides. By adopting Memory Controller TLB (MTLB) from the shadow memory, it allows superpages to be composed of arbitrary physical pages. The entry structure of the partial-subblock TLB applied for the processor TLB enables all invalid address mappings to be identified inside CPU, which reduces the overhead of handling invalid mappings. In addition, cache flushing which is required when a mapping of shadow address to physical address is destroyed (e.g. due to paging) can be replaced just by resetting the corresponding valid bit in the processor TLB. At last, the per-base-page reference bits in the processor TLB make the page replacement policy of the operating system more efficient.

In simulation with six benchmarks, our mechanism generates only 27% of TLB misses compared to the single-page-size TLB. With a detailed analysis, it is shown to be evident that the efficiency of our mechanism is magnified in real computing environment where multitasking and applications of large sizes are ordinary cases.