research-article

Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors

Authors:

Ashwini Kulkarni,

Hemangee K. KapoorAuthors Info & Claims

GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSI

Pages 487 - 492

https://doi.org/10.1145/3386263.3406951

Published: 07 September 2020 Publication History

Abstract

The continuous rise of on-chip components like cores and caches has brought enormous computing capabilities at the cost of high leakage power and temperature. A recent study has shown a substantial spatial temperature variance in modern large on-chip caches. This high temperature elevates the cooling cost and becomes responsible for the thermal breakdown of the chip. One solution to reduce the leakage is the use of non-volatile memory (NVM) like STT-RAM. Other includes incorporating the concept of dark silicon. In this paper, we amalgamate the idea of using STT-RAM in the last level cache (LLC) and the dark silicon approach to shut down certain cache ways to leverage the benefits from both. We address the downsides like higher access latencies of STT-RAM by the use of hybrid cache (SRAM + STT-RAM) and weak endurance of the STT-RAM by wear leveling. We propose a system to handle three different temperature thresholds (high, medium, and low) by appropriately selecting the type of cache ways to be powered off. The proposed system delivers up to 5.38 K reduction in temperature compared to the baseline, 93% reduction in leakage power with an EDP gain up to 92%.

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References

[1]

Alessandro Bardine et al. 2007 a. Analysis of static and dynamic energy consumption in nuca caches: Initial results. In MEDEA. ACM, 105--112.

[2]

Alankar V Umdekar et al. 2018. Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors. In VLSID. IEEE.

[3]

Christian Bienia et al. 2008a. The PARSEC benchmark suite: Characterization and architectural implications. In PACT. ACM, 72--81.

[4]

Dmytro Apalkov et al. 2013a. Spin-transfer torque magnetic random access memory (STT-MRAM). JETC, Vol. 9, 2 (2013), 13.

[5]

Guangyu Sun et al. 2012a. Performance/thermal-aware design of 3D-stacked L2 caches for CMPs. TODAES, Vol. 17, 2 (2012), 13.

[6]

Hadi Esmaeilzadeh et al. 2011a. Dark silicon and the end of multicore scaling. In ISCA. IEEE, 365--376.

[7]

Ing-Chao Lin et al. 2015a. High-Endurance Hybrid Cache Design in CMP Architecture With Cache Partitioning and Access-Aware Policies. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, 10 (2015), 2149--2161.

[8]

Ja Chun Ku et al. 2007 b. Thermal management of on-chip caches through power density minimization. TVLSI, Vol. 15, 5 (2007), 592--604.

[9]

Joonho Kong et al. 2012b. Recent thermal management techniques for microprocessors. CSUR, Vol. 44, 3 (2012), 13.

[10]

Jue Wang et al. 2013b. i 2 WAP: Improving non-volatile cache lifetime by reducing inter-and intra-set write variations. In HPCA. IEEE, 234--245.

[11]

Kyriakos Stavrou et al. 2005. TSIC: Thermal Scheduling Simulator for Chip Multiprocessors, Vol. 3746. 589--599. https://doi.org/10.1007/11573036_56

[12]

Mengquan Li et al. 2017. Chip temperature optimization for dark silicon many-core systems. TCAD, Vol. 37, 5 (2017), 941--953.

[13]

Mesut Meterelliyoz et al. 2009a. Analysis of SRAM and eDRAM cache memories under spatial temperature variations. IEEE TCAD, Vol. 29, 1 (2009), 2--13.

[14]

Muhammad Shafique et al. 2014a. Dark silicon as a challenge for hardware/software co-design: Invited special session paper. In CODES. ACM, 13.

[15]

Muhammad Shafique et al. 2016. Computing in the dark silicon era: Current trends and research challenges. Design & Test, Vol. 34, 2 (2016), 8--23.

[16]

Nathan Binkert et al. 2011b. The gem5 simulator. SIGARCH, Vol. 39, 2 (2011), 1--7.

Digital Library

[17]

Raid Ayoub et al. 2010. Performance and energy efficient cache migrationapproach for thermal management in embedded systems. In GLSVLSI. ACM, 365--368.

[18]

Runjie Zhang et al. 2015b. Hotspot 6.0: Validation, acceleration and extension. University of Virginia, Tech. Rep (2015).

[19]

Shounak Chakraborty et al. 2019. Exploring the Role of Large Centralised Caches in Thermal Efficient Chip Design. ACM Trans. Des. Autom. Electron. Syst., Vol. 24, 5 (2019).

[20]

S. Li et al. 2009b. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In MICRO. 469--480.

[21]

Sparsh Mittal et al. 2014b. LastingNVCache: A technique for improving the lifetime of non-volatile caches. In ISVLSI. IEEE, 534--540.

[22]

Sobhan Niknam et al. 2015c. Energy efficient 3D Hybrid processor-memory architecture for the dark silicon age. In ReCoSoC. IEEE, 1--8.

[23]

Shyamkumar Thoziyoor et al. 2008b. CACTI 5.1. Technical Report. Technical Report, HP Labs.

[24]

V. Hanumaiah et al. 2009c. Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control. In ICCAD. 310--313.

[25]

Wei Zang et al. 2013c. A survey on cache tuning from a power/energy perspective. CSUR, Vol. 45, 3 (2013), 32.

[26]

Xiangyu Dong et al. 2012c. NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory. TCAD, Vol. 31 (2012), 994--1007.

[27]

Xiaoxia Wu et al. 2009 d. Hybrid cache architecture with disparate memory technologies. In SIGARCH, Vol. 37. ACM, 34--45.

[28]

Yu-Ting Chen et al. 2012 d. Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design. In DATE. EDA Consortium, 45--50.

Cited By

Ni MChen LHao XLiu CZhang YPan L(2022)Write-Awareness Prefetching for Non-Volatile Cache in Energy-Constrained IoT DeviceIEICE Electronics Express10.1587/elex.19.20210499Online publication date: 2022
https://doi.org/10.1587/elex.19.20210499
Kulkarni AMahajan S(2022)Improving Effectiveness of Parallel Processing with Smart Cache Utilization for Energy Saving and Temperature Reduction In Chip Multiprocessors2022 IEEE 4th International Conference on Cybernetics, Cognition and Machine Learning Applications (ICCCMLA)10.1109/ICCCMLA56841.2022.9989285(128-132)Online publication date: 8-Oct-2022
https://doi.org/10.1109/ICCCMLA56841.2022.9989285

Index Terms

Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors
1. Hardware
  1. Power and energy
    1. Thermal issues
      1. Temperature control

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cover image ACM Other conferences

GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSI

September 2020

597 pages

ISBN:9781450379441

DOI:10.1145/3386263

General Chairs:
Tinoosh Mohsenin
University of Maryland, Baltimore County, USA
,
Weisheng Zhao
Beihang University, China
,
Program Chairs:
Yiran Chen
Duke University, USA
,
Onur Mutlu
ETH Zurich, Switzerland

Copyright © 2020 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

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Published: 07 September 2020

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GLSVLSI '20

GLSVLSI '20: Great Lakes Symposium on VLSI 2020

September 7 - 9, 2020

Virtual Event, China

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Ni MChen LHao XLiu CZhang YPan L(2022)Write-Awareness Prefetching for Non-Volatile Cache in Energy-Constrained IoT DeviceIEICE Electronics Express10.1587/elex.19.20210499Online publication date: 2022
https://doi.org/10.1587/elex.19.20210499
Kulkarni AMahajan S(2022)Improving Effectiveness of Parallel Processing with Smart Cache Utilization for Energy Saving and Temperature Reduction In Chip Multiprocessors2022 IEEE 4th International Conference on Cybernetics, Cognition and Machine Learning Applications (ICCCMLA)10.1109/ICCCMLA56841.2022.9989285(128-132)Online publication date: 8-Oct-2022
https://doi.org/10.1109/ICCCMLA56841.2022.9989285

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