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Sub-10-μm Coil Design for Multi-Hop Inductive Coupling Interface

Published: 29 January 2021 Publication History

Abstract

Sub-10-μm on-chip coils are designed and prototyped for the multi-hop inductive coupling interface in a 40-nm CMOS. Multi-layer coils and a new receiver circuit are employed to compensate the decrease of the coupling coefficient due to the small coil size. The prototype emulates a 3D stacked module with 8 dies in a 7-nm CMOS and shows that a 0.1-pJ/bit and 41-Tb/s/mm2 inductive coupling interface is achievable.

References

[1]
D. U. Lee, et al., IEEE JSSC, Jan. 2015.
[2]
D. Ditzel, et al., Hot Chips, Aug. 2014.
[3]
K. Ueyoshi et al., IEEE JSSC, Jan. 2019.
[4]
T. Ohba, IEEE IITC, June. 2010.
[5]
T. Fukushima, et al., IEEE Trans. On CPMT, Dec. 2011.
[6]
K. Sohn, et al., IEEE JSSC, Jan. 2017.
[7]
K. Shiba, et al., IEEE ISCAS, Oct. 2020.

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cover image ACM Conferences
ASPDAC '21: Proceedings of the 26th Asia and South Pacific Design Automation Conference
January 2021
930 pages
ISBN:9781450379991
DOI:10.1145/3394885
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 29 January 2021

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ASPDAC '21 Paper Acceptance Rate 111 of 368 submissions, 30%;
Overall Acceptance Rate 466 of 1,454 submissions, 32%

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