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Instruction path coprocessors

Authors:

John Paul ShenAuthors Info & Claims

ISCA '00: Proceedings of the 27th annual international symposium on Computer architecture

Pages 270 - 281

https://doi.org/10.1145/339647.339694

Published: 01 May 2000 Publication History

Abstract

This paper presents the concept of an Instruction Path Coprocessor (I-COP), which is a programmable on-chip coprocessor, with its own mini-instruction set, that operates on the core processor's instructions to transform them into an internal format that can be more efficiently executed. It is located off the critical path of the core processor to ensure that it does not negatively impact the core processor's cycle time or pipeline depth. An I-COP is highly versatile and can be used to implement different types of instruction transformations to enhance the IPC of the core processor. We study four potential applications of the I-COP to demonstrate the feasibility of this concept and investigate the design issues of such a coprocessor. A prototype instruction set for the I-COP is presented along with an implementation framework that facilitates achieving high I-COP performance. Initial results indicate that the I-COP is able to efficiently implement the trace cache fill unit as well as the register move, stride data prefetching and linked data structure prefetching trace optimizations.

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Liu FAhn HBeard SOh TAugust D(2015)DynaSpAMACM SIGARCH Computer Architecture News10.1145/2872887.275041443:3S(541-553)Online publication date: 13-Jun-2015
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Liu FAhn HBeard SOh TAugust DMarr DAlbonesi D(2015)DynaSpAMProceedings of the 42nd Annual International Symposium on Computer Architecture10.1145/2749469.2750414(541-553)Online publication date: 13-Jun-2015
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Lee EZilles CSoffa MDuesterwald E(2008)Branch-on-randomProceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization10.1145/1356058.1356070(84-93)Online publication date: 6-Apr-2008
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Index Terms

Instruction path coprocessors
1. Computer systems organization
  1. Architectures
    1. Other architectures
2. Hardware
  1. Robustness
    1. Fault tolerance
    2. Hardware reliability

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cover image ACM Conferences

ISCA '00: Proceedings of the 27th annual international symposium on Computer architecture

June 2000

327 pages

ISBN:1581132328

DOI:10.1145/339647

Chairmen:
Alan Berenbaum
Lucent Technologies
,
Joel Emer
Compaq Computer Corp.

ACM SIGARCH Computer Architecture News Volume 28, Issue 2
Special Issue: Proceedings of the 27th annual international symposium on Computer architecture (ISCA '00)
May 2000
325 pages
ISSN:0163-5964
DOI:10.1145/342001
Chairmen:
Alan Berenbaum
Lucent Technologies, Berkeley Heights, NJ
,
Joel Emer
Compaq Computer Corp., Palo Alto, CA
Issue’s Table of Contents

Copyright © 2000 ACM.

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Published: 01 May 2000

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Cited By

Liu FAhn HBeard SOh TAugust D(2015)DynaSpAMACM SIGARCH Computer Architecture News10.1145/2872887.275041443:3S(541-553)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2872887.2750414
Liu FAhn HBeard SOh TAugust DMarr DAlbonesi D(2015)DynaSpAMProceedings of the 42nd Annual International Symposium on Computer Architecture10.1145/2749469.2750414(541-553)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2749469.2750414
Lee EZilles CSoffa MDuesterwald E(2008)Branch-on-randomProceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization10.1145/1356058.1356070(84-93)Online publication date: 6-Apr-2008
https://dl.acm.org/doi/10.1145/1356058.1356070
Stitt GVahid F(2008)Binary synthesisACM Transactions on Design Automation of Electronic Systems10.1145/1255456.125547112:3(1-30)Online publication date: 22-May-2008
https://dl.acm.org/doi/10.1145/1255456.1255471
Hu SSmith J(2006)Reducing Startup Time in Co-Designed Virtual MachinesACM SIGARCH Computer Architecture News10.1145/1150019.113651034:2(277-288)Online publication date: 1-May-2006
https://dl.acm.org/doi/10.1145/1150019.1136510
Hu SSmith J(2006)Reducing Startup Time in Co-Designed Virtual MachinesProceedings of the 33rd annual international symposium on Computer Architecture10.1109/ISCA.2006.33(277-288)Online publication date: 17-Jun-2006
https://dl.acm.org/doi/10.1109/ISCA.2006.33
Kim ILipasti M(2003)Macro-op SchedulingProceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture10.5555/956417.956563Online publication date: 3-Dec-2003
https://dl.acm.org/doi/10.5555/956417.956563
Slechta BCrowe DFahs BFertig MMuthler GQuek JSpadini FPatel SLumetta S(2003)Dynamic Optimization of Micro-OperationsProceedings of the 9th International Symposium on High-Performance Computer Architecture10.5555/822080.822824Online publication date: 8-Feb-2003
https://dl.acm.org/doi/10.5555/822080.822824
Chen HHsu WLu JYew PChen DJohnson RConte THwu W(2003)Dynamic trace selection using performance monitoring hardware samplingProceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization10.5555/776261.776270(79-90)Online publication date: 23-Mar-2003
https://dl.acm.org/doi/10.5555/776261.776270
Kim HSmith JJohnson RConte THwu W(2003)Dynamic binary translation for accumulator-oriented architecturesProceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization10.5555/776261.776264(25-35)Online publication date: 23-Mar-2003
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