Synthesis for mixed CMOS/PTL logic (poster paper)
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References
[1]
K. Yano, Y. Sasaki, K. Rikino, and K. Seki, "Top-Down Pass Transistor Logic Design," IEEE J. Solid-State Circuits, vol. 31, no. 6, pp. 792-803, June 1996.
[2]
P. Buch, A. Narayan, R. Newton, and A. Sangiovanni-Vincentelli, "On Synthesizing Pass Transistor Logic," in Intl. Workshop on Logic Synthesis, 1997.
[3]
V Bertacco, S. Minato, P. Verpaetse, L. Benini, and G. De Micheli, "Decision diagrams and pass transistor logic synthesis," in Intl. Workshop on Logic Synthesis, 1997.
[4]
C. Yang, V. Singhal, and M. Ciesielski, "BDD Decomposition for Efficient Logic Synthesis," in International Conference on Computer Design, 1999, pp. 626-631.
[5]
S. Yamashita, K. Yano, Y. Sasaki, Y. Akita, H Chikata, K. Rikino, and K Seki, "Pass- Transistor/CMOS Collaborated Logic: The Best of Both Worlds," in Symposium on VLSI Circuits Digest of Technical Papers, 1997, pp. 31-32.
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- Synthesis for mixed CMOS/PTL logic (poster paper)
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Published: 01 January 2000
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