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Pomegranate: a fully scalable graphics architecture

Published: 01 July 2000 Publication History

Abstract

Pomegranate is a parallel hardware architecture for polygon rendering that provides scalable input bandwidth, triangle rate, pixel rate, texture memory and display bandwidth while maintaining an immediate-mode interface. The basic unit of scalability is a single graphics pipeline, and up to 64 such units may be combined. Pomegranate's scalability is achieved with a novel “sort-everywhere” architecture that distributes work in a balanced fashion at every stage of the pipeline, keeping the amount of work performed by each pipeline uniform as the system scales. Because of the balanced distribution, a scalable network based on high-speed point-to-point links can be used for communicating between the pipelines.
Pomegranate uses the network to load balance triangle and fragment work independently, to provide a shared texture memory and to provide a scalable display system. The architecture provides one interface per pipeline for issuing ordered, immediate-mode rendering commands and supports a parallel API that allows multiprocessor applications to exactly order drawing commands from each interface. A detailed hardware simulation demonstrates performance on next-generation workloads. Pomegranate operates at 87-99% parallel efficiency with 64 pipelines, for a simulated performance of up to 1.10 billion triangles per second and 21.8 billion pixels per second.

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cover image ACM Conferences
SIGGRAPH '00: Proceedings of the 27th annual conference on Computer graphics and interactive techniques
July 2000
547 pages
ISBN:1581132085

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ACM Press/Addison-Wesley Publishing Co.

United States

Publication History

Published: 01 July 2000

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Author Tags

  1. graphics hardware
  2. parallel computing

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SIGGRAPH '00 Paper Acceptance Rate 59 of 304 submissions, 19%;
Overall Acceptance Rate 1,822 of 8,601 submissions, 21%

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Cited By

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  • (2021)CHOPIN: Scalable Graphics Rendering in Multi-GPU Systems via Parallel Image Composition2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA51647.2021.00065(709-722)Online publication date: Feb-2021
  • (2020)Analyzing and Leveraging Shared L1 Caches in GPUsProceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques10.1145/3410463.3414623(161-173)Online publication date: 30-Sep-2020
  • (2018)On-the-fly Vertex Reuse for Massively-Parallel Software Geometry ProcessingProceedings of the ACM on Computer Graphics and Interactive Techniques10.1145/32333031:2(1-17)Online publication date: 24-Aug-2018
  • (2018)A high-performance software graphics pipeline architecture for the GPUACM Transactions on Graphics10.1145/3197517.320137437:4(1-15)Online publication date: 30-Jul-2018
  • (2017)GPUpdProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3123968(574-586)Online publication date: 14-Oct-2017
  • (2017)Effective static bin patterns for sort-middle renderingProceedings of High Performance Graphics10.1145/3105762.3105777(1-10)Online publication date: 28-Jul-2017
  • (2016)Supporting Static Binding in Stream Rewriting for Heterogeneous Many-Core Architectures2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)10.1109/MCSoC.2016.26(273-280)Online publication date: Sep-2016
  • (2015)PikoACM Transactions on Graphics10.1145/276697334:4(1-13)Online publication date: 27-Jul-2015
  • (2013)A Programmable Graphics Processor based on Partial Stream RewritingComputer Graphics Forum10.1111/cgf.1224032:7(325-334)Online publication date: 25-Nov-2013
  • (2011)BibliographyReal-Time Rendering, Third Edition10.1201/b10644-23(921-1002)Online publication date: Mar-2011
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