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Vector instruction selection for digital signal processors using program synthesis

Authors:

Maaz Bin Safeer Ahmad,

Alexander J. Root,

Alvin CheungAuthors Info & Claims

ASPLOS '22: Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

Pages 1004 - 1016

https://doi.org/10.1145/3503222.3507714

Published: 22 February 2022 Publication History

Abstract

Instruction selection, whereby input code represented in an intermediate representation is translated into executable instructions from the target platform, is often the most target-dependent component in optimizing compilers. Current approaches include pattern matching, which is brittle and tedious to design, or search-based methods, which are limited by scalability of the search algorithm. In this paper, we propose a new algorithm that first abstracts the target platform instructions into high-level uber-instructions, with each uber-instruction unifying multiple concrete instructions from the target platform. Program synthesis is used to lift input code sequences into semantically equivalent sequences of uber-instructions and then to lower from uber-instructions to machine code. Using 21 real-world benchmarks, we show that our synthesis-based instruction selection algorithm can generate instruction sequences for a hardware target, with the synthesized code performing up to 2.1x faster as compared to code generated by a professionally-developed optimizing compiler for the same platform.

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Cited By

Gong LWang JCheung ALarson K(2024)ADELTProceedings of the Thirty-Third International Joint Conference on Artificial Intelligence10.24963/ijcai.2024/694(6279-6287)Online publication date: 3-Aug-2024
https://dl.acm.org/doi/10.24963/ijcai.2024/694
Kothari ANoor AXu MUddin HBaronia DBaziotis SAdve VMendis CSengupta STsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)Hydride: A Retargetable and Extensible Synthesis-based Compiler for Modern Hardware ArchitecturesProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3620665.3640385(514-529)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3620665.3640385
Thomas SBornholt JTsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)Automatic Generation of Vectorizing Compilers for Customizable Digital Signal ProcessorsProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 110.1145/3617232.3624873(19-34)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3617232.3624873
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Index Terms

Vector instruction selection for digital signal processors using program synthesis
1. Software and its engineering

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cover image ACM Conferences

ASPLOS '22: Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

February 2022

1164 pages

ISBN:9781450392051

DOI:10.1145/3503222

General Chairs:
Babak Falsafi
EPFL, Switzerland
,
Michael Ferdman
Stony Brook University, USA
,
Program Chairs:
Shan Lu
University of Chicago, USA
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Tom Wenisch
University of Michigan, USA / Google, USA

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Published: 22 February 2022

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ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

February 28 - March 4, 2022

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Cited By

Gong LWang JCheung ALarson K(2024)ADELTProceedings of the Thirty-Third International Joint Conference on Artificial Intelligence10.24963/ijcai.2024/694(6279-6287)Online publication date: 3-Aug-2024
https://dl.acm.org/doi/10.24963/ijcai.2024/694
Kothari ANoor AXu MUddin HBaronia DBaziotis SAdve VMendis CSengupta STsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)Hydride: A Retargetable and Extensible Synthesis-based Compiler for Modern Hardware ArchitecturesProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3620665.3640385(514-529)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3620665.3640385
Thomas SBornholt JTsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)Automatic Generation of Vectorizing Compilers for Customizable Digital Signal ProcessorsProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 110.1145/3617232.3624873(19-34)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3617232.3624873
VanHattum APardeshi MFallin CSampson ABrown FTsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)Lightweight, Modular Verification for WebAssembly-to-Native Instruction SelectionProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 110.1145/3617232.3624862(231-248)Online publication date: 27-Apr-2024
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McMichen TGreiner NZhong PSossai FPatel ACampanoni SGrosser TDubach CSteuwer MXue JOttoni GQuintão Pereira F(2024)Representing Data Collections in an SSA FormProceedings of the 2024 IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO57630.2024.10444817(308-321)Online publication date: 2-Mar-2024
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Root AAhmad MSharlet DAdams AKamil SRagan-Kelley JAamodt TSwift MJerger N(2023)Fast Instruction Selection for Fast Digital Signal ProcessingProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 410.1145/3623278.3624768(125-137)Online publication date: 25-Mar-2023
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Niu WGuan JShen XWang YAgrawal GRen BHardavellas NCampanoni SGrot BKarpuzcu U(2022)GCD2: A Globally Optimizing Compiler for Mapping DNNs to Mobile DSPsProceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO56248.2022.00044(512-529)Online publication date: 1-Oct-2022
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