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Survey on Architectural Attacks: A Unified Classification and Attack Model

Published: 15 September 2023 Publication History

Abstract

According to the World Economic Forum, cyberattacks are considered as one of the most important sources of risk to companies and institutions worldwide. Attacks can target the network, software, and/or hardware. Over the years, much knowledge has been developed to understand and mitigate cyberattacks. However, new threats have appeared in recent years regarding software attacks that exploit hardware vulnerabilities. This article defines these attacks as architectural attacks. Today, both industry and academia have only limited comprehension of architectural attacks, which represents a critical issue for the design of future systems. To this end, this work proposes a new taxonomy, a new attack model, and a complete survey of existing architectural attacks. As a result, it provides the tools to understand architectural attacks in more depth and to start building improved designs and protection mechanisms.

References

[1]
Fortune Business Insights. 2022. Cyber Security Market Size. Retrieved from https://www.fortunebusinessinsights.com/industry-reports/cyber-security-market-101165
[2]
Cybersecurity and Infrastructure security agency. 2021. 5G Security and Resilience. Retrieved in 2022 from https://www.cisa.gov/5g.
[3]
Alvaro A. Cárdenas, Tanya Roosta, Gelareh Taban, and Shankar Sastry. 2008. Cyber security basic defenses and attack trends. Homeland Security Technology Challenges (2008), 73–101.
[4]
Julian Jang-Jaccard and Surya Nepal. 2014. A survey of emerging threats in cybersecurity. J. Comput. System Sci. 80, 5 (2014), 973–993. DOI:
[5]
Vijay Tiwari and Dwivedi. 2016. Analysis of cyber attack vectors. In Proceedings of the 2016 International Conference on Computing, Communication and Automation (ICCCA’16). IEEE. DOI:
[6]
Yoohwan Kim, Wing Cheong Lau, Mooi Choo Chuah, and H. J. Chao. 2006. PacketScore: A statistics-based packet filtering scheme against distributed denial-of-service attacks. IEEE Trans. Dependable Secure Comput. 3, 2 (2006), 141–155. DOI:
[7]
Huanyu Wang, Henian Li, Fahim Rahman, Mark M. Tehranipoor, and Farimah Farahmandi. 2022. SoFI: Security property-driven vulnerability assessments of ICs against fault-injection attacks. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 41, 3 (2022), 452–465. DOI:
[8]
Andrey Bogdanov, Thomas Eisenbarth, Christof Paar, and Malte Wienecke. 2010. Differential cache-collision timing attacks on AES with applications to embedded CPUs. In Topics in Cryptology (CT-RSA’10), Josef Pieprzyk (Ed.). Springer, Berlin, 235–251.
[9]
Anne Canteaut, Cédric Lauradoux, and André Seznec. 2006. Understanding Cache Attacks. Research Report RR-5881. INRIA. https://hal.inria.fr/inria-00071387.
[10]
Tianwei Zhang and Ruby Lee. 2014. Secure Cache Modeling for Measuring Side-Channel Leakage. Technical Report, Princeton University.
[11]
Paul Kocher, Daniel Genkin, Daniel Gruss, Werner Haas, Mike Hamburg, Moritz Lipp, Stefan Mangard, Thomas Prescher, Michael Schwarz, and Yuval Yarom. 2018. Spectre attacks: Exploiting speculative execution. IEEE Symposium on Security and Privacy (SP), San Francisco, CA, USA, 1–19. DOI:
[12]
Qian Ge, Yuval Yarom, David Cock, and Gernot Heiser. 2018. A survey of microarchitectural timing attacks and countermeasures on contemporary hardware. J. Cryptogr. Eng. 8, 1 (2018), 1–27.
[13]
Yangdi Lyu and Prabhat Mishra. 2018. A survey of side-channel attacks on caches and countermeasures. J. Hardware Syst. Sec. 2, 1 (2018), 33–50.
[14]
Shuwen Deng, Wenjie Xiong, and Jakub Szefer. 2019. Analysis of Secure Caches using a Three-Step Model for Timing-Based Attacks. Cryptology ePrint Archive, Report 2019/167. Retrieved from https://eprint.iacr.org/2019/167.
[15]
Yuval Yarom and Katrina Falkner. 2014. FLUSH+RELOAD: A high resolution, low noise, L3 cache side-channel attack. In Proceedings of the 23rd USENIX.
[16]
Claudio Canella, Jo Van Bulck, Michael Schwarz, Moritz Lipp, Benjamin Von Berg, Philipp Ortner, Frank Piessens, Dmitry Evtyushkin, and Daniel Gruss. 2019. A systematic evaluation of transient execution attacks and defenses. In Proceedings of the 28th USENIX Conference on Security Symposium(SEC’19). ACM.
[17]
Paul Kocher, Jann Horn, Anders Fogh, Daniel Genkin, Daniel Gruss, Werner Haas, Moritz Lipp, Stefan Mangard, Thomas Prescher, Michael Schwarz, and Yuval Yarom. 2019. Spectre attacks: Exploiting speculative execution. In IEEE SP.
[18]
Dag Arne Osvik, Adi Shamir, and Eran Tromer. 2006. Cache attacks and countermeasures: The case of AES. In CT-RSA 2006. Springer, 1–20.
[19]
David Budgen and Pearl Brereton. 2006. Performing systematic literature reviews in software engineering. In Proceedings of the 28th International Conference on Software Engineering(ICSE’06). Association for Computing Machinery, New York, NY, 1051–1052. DOI:
[20]
Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil, Behrad Niazmand, Tara Ghasempouri, Jaan Raik, and Johanna Sepülveda. 2020. LiD-CAT: A lightweight detector for cache attacks. In Proceedings of the 2020 IEEE European Test Symposium (ETS’20), 1–6. DOI:
[21]
Daniel J. Bernstein. 2005. Cache Timing Attacks on AES. Retrieved December 12, 2016.
[22]
Joseph Bonneau and Ilya Mironov. 2006. Cache-collision timing attacks against AES. In CHES. 201–215.
[23]
Christopher Domas. 2017. Breaking the x86 ISA. Retrieved in 2022 from https://www.blackhat.com/docs/us-17/thursday/us-17-Domas-Breaking-The-x86-ISA.pdf
[24]
Philipp Koppe, Benjamin Kollenda, Marc Fyrbiak, Christian Kison, Robert Gawlik, Christof Paar, and Thorsten Holz. 2017. Reverse engineering \(\times\) 86 processor microcode. In Proceedings of the 26th USENIX Conference on Security Symposium(SEC’17), 1163–1180.
[25]
Henry Wong, Misel-Myrto Papadopoulou, Maryam Sadooghi-Alvandi, and Andreas Moshovos. 2010. Demystifying GPU microarchitecture through microbenchmarking. In Proceedings of the 2010 IEEE International Symposium on Performance Analysis of Systems Software (ISPASS’10). IEEE, 235–246. DOI:
[26]
Christopher Domas. 2018. GOD MODE unlocked: Hardware backdoors in x86 CPUs. Retrieved in 2022 from https://i.blackhat.com/us-18/Thu-August-9/us-18-Domas-God-Mode-Unlocked-Hardware-Backdoors-In-x86-CPUs.pdf
[27]
Andreas Abel and Jan Reineke. 2013. Measurement-based modeling of the cache replacement policy. In Proceedings of the 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS’13). IEEE, 65–74. DOI:
[28]
C. L. Coleman and J. W. Davidson. 2001. Automatic memory hierarchy characterization. In Proceedings of the 2001 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS’01). IEEE, New York, NY, 103–110. DOI:
[29]
Jack Dongarra, Shirley Moore, Philip Mucci, Keith Seymour, and Haihang You. 2004. Accurate cache and TLB characterization using hardware counters. In Computational Science (ICCS’04), Marian Bubak, Geert Dick van Albada, Peter M. A. Sloot, and Jack Dongarra (Eds.). Springer, Berlin, Heidelberg, 432–439.
[30]
Mohamed Hassan, Anirudh M. Kaushik, and Hiren Patel. 2015. Reverse-engineering embedded memory controllers through latency-based analysis. In Proceedings of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium. IEEE, 297–306. DOI:
[31]
Mohamed Hassan, Anirudh M. Kaushik, and Hiren Patel. 2018. Exposing implementation details of embedded DRAM memory controllers through latency-based analysis. ACM Trans. Embed. Comput. Syst. 17, 5 (Oct. 2018), Article 90, 25 pages. DOI:
[32]
Matthias Jung, Carl C. Rheinlä, Christian Weis, and Norbert Wehn. 2016. Reverse engineering of DRAMs: Row hammer with crosshair. In Proceedings of the 2nd International Symposium on Memory Systems. Association for Computing Machinery, New York, NY, 471–476. 9781450343053.
[33]
S. Evain and J.-P. Diguet. 2005. From NoC security analysis to design solutions. In Proceedings of the IEEE Workshop on Signal Processing Systems Design and Implementation, 2005, 166–171. DOI:
[34]
One Aleph. 1996. Smashing the stack for fun and profit. Retrieved in 2022 from http://www.shmoo.com/phrack/Phrack49/p49-14.
[35]
Steven Alexander. 2005. Defeating compiler-level buffer overflow protection. The USENIX Magazine; login (2005). Retrieved in 2022 from https://www.usenix.org/publications/login/june-2005-volume-30-number-3/defeating-compiler-level-buffer-overflow-protection
[36]
Arash Baratloo, Navjot Singh, and Timothy K. Tsai. 2000. Transparent run-time defense against stack-smashing attacks. In Proceedings of the USENIX Annual Technical Conference, General Track, 251–262.
[37]
Sandeep Bhatkar, Daniel C. DuVarney, and Ron Sekar. 2003. Address obfuscation: An efficient approach to combat a broad range of memory error exploits. In PRoceedings of the USENIX Security Symposium, Vol. 12, 291–301.
[38]
Nicholas Carlini, Antonio Barresi, Mathias Payer, David Wagner, and Thomas R. Gross. 2015. Control-flow bending: On the effectiveness of control-flow integrity. In Proceeding of the USENIX Security Symposium, 161–176.
[39]
Crispan Cowan, Calton Pu, Dave Maier, Jonathan Walpole, Peat Bakke, Steve Beattie, Aaron Grier, Perry Wagle, Qian Zhang, and Heather Hinton. 1998. Stackguard: Automatic adaptive detection and prevention of buffer-overflow attacks. In Proceedings of the USENIX Security Symposium, Vol. 98. 63–78.
[40]
Yongje Lee, Ingoo Heo, Dongil Hwang, Kyungmin Kim, and Yunheung Paek. 2015. Towards a practical solution to detect code reuse attacks on ARM mobile devices. In Proceedings of the 4th Workshop on Hardware and Architectural Support for Security and Privacy(HASP’15). Association for Computing Machinery, New York, NY, Article 3, 8. DOI:
[41]
Hilmi Ozdoganoglu, T. N. Vijaykumar, Carla E. Brodley, Benjamin A. Kuperman, and Ankit Jalote. 2006. SmashGuard: A hardware solution to prevent security attacks on the function return address. IEEE Trans. Comput. 55, 10 (2006), 1271–1285.
[42]
Gerardo Richarte. 2002. Four different tricks to bypass stackshield and stackguard protection. Retrieved in 2022 from https://www.cs.purdue.edu/homes/xyzhang/spring07/Papers/defeat-stackguard.pdf
[43]
Hovav Shacham, Matthew Page, Ben Pfaff, Eu-Jin Goh, Nagendra Modadugu, and Dan Boneh. 2004. On the effectiveness of address-space randomization. In Proceedings of the 11th ACM conference on Computer and Communications Security. ACM, 298–307.
[44]
Nathan P. Smith. 1997. Stack smashing vulnerabilities in the UNIX operating system. Retrieved in 2022 from https://www.zdnet.com/article/stackclash-vulnerabilities-rip-root-holes-in-linux-systems/
[45]
Ana Nora Sovarel, David Evans, and Nathanael Paul. 2005. Where’s the FEEB? The effectiveness of instruction set randomization. In Proceedings of the USENIX Security Symposium, Vol. 10.
[46]
Daniel Gruss, Moritz Lipp, Michael Schwarz, Richard Fellner, Clémentine Maurice, and Stefan Mangard. 2017. KASLR is dead: Long live KASLR. In Proceedings of the International Symposium on Engineering Secure Software and Systems. Springer, 161–176.
[47]
Daniel Gruss, Clémentine Maurice, and Stefan Mangard. 2016. Rowhammer. js: A remote software-induced fault attack in javascript. In Proceedings of the International Conference on Detection of Intrusions and Malware, and Vulnerability Assessment. Springer, 300–321.
[48]
Yeongjin Jang, Jaehyuk Lee, Sangho Lee, and Taesoo Kim. 2017. SGX-Bomb: Locking down the processor via Rowhammer attack. In Proceedings of the 2nd Workshop on System Software for Trusted Execution. ACM, 5.
[49]
Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, and Onur Mutlu. 2014. Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors. In ACM SIGARCH Computer Architecture News, Vol. 42. IEEE Press, IEEE, 361–372.
[50]
Moritz Lipp, Misiker Tadesse Aga, Michael Schwarz, Daniel Gruss, Clémentine Maurice, Lukas Raab, and Lukas Lamster. 2020. Nethammer: Inducing rowhammer faults through network requests. IEEE European Symposium on Security and Privacy Workshops (EuroSPW), Genoa, Italy. 710–719, DOI:
[51]
Peter Pessl, Daniel Gruss, Clémentine Maurice, Michael Schwarz, and Stefan Mangard. 2016. DRAMA: Exploiting DRAM addressing for cross-CPU attacks. In Proceedings of the USENIX Security Symposium, 565–581.
[52]
Andrei Tatar, Radhesh Krishnan, Elias Athanasopoulos, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi. 2018. Throwhammer: Rowhammer attacks over the network and defenses. In Proceedings of the 2018 USENIX Annual Technical Conference. USENIX Association.
[53]
Victor Van Der Veen, Yanick Fratantonio, Martina Lindorfer, Daniel Gruss, Clémentine Maurice, Giovanni Vigna, Herbert Bos, Kaveh Razavi, and Cristiano Giuffrida. 2016. Drammer: Deterministic Rowhammer attacks on mobile platforms. In Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security. ACM, 1675–1689.
[54]
A. Ben Achballah, S. Ben Othman, and S. Ben Saoud. 2017. Toward on hardware firewalling of networks-on-chip based systems. In Proceedings of the 2017 International Conference on Advanced Systems and Electric Technologies (IC_ASET’17). IEEE, 7–13. DOI:
[55]
T. Boraten and A. K. Kodi. 2016. Mitigation of denial of service attack with hardware trojans in NoC architectures. In Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS’16). IEEE, 1091–1100. DOI:
[56]
L. L. Caimi, V. Fochi, E. Wachter, D. Munhoz, and F. G. Moraes. 2017. Activation of secure zones in many-core systems with dynamic rerouting. In Proceedings of the 2017 IEEE International Symposium on Circuits and Systems (ISCAS’17). IEEE, 1–4. DOI:
[57]
Leandro Fiorin, Gianluca Palermo, and Cristina Silvano. 2008. A security monitoring service for NoCs. In Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis(CODES+ISSS’08). ACM, New York, NY, 197–202. DOI:
[58]
Leandro Fiorin, Cristina Silvano, and Mariagiovanna Sami. 2007. Security aspects in networks-on-chips: Overview and proposals for secure implementations. In Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD’07). IEEE, 539–542.
[59]
M. D. Grammatikakis, K. Papadimitriou, P. Petrakis, A. Papagrigoriou, G. Kornaros, I. Christoforakis, O. Tomoutzoglou, G. Tsamis, and M. Coppola. 2015. Security in MPSoCs: A NoC firewall and an evaluation framework. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 34, 8 (2015), 1344–1357. DOI:
[60]
Dirk Grunwald and Soraya Ghiasi. 2002. Microarchitectural denial of service: Insuring microarchitectural fairness. In Proceedings of the 35th Annual ACM/IEEE International Symposium on Microarchitecture(MICRO 35). IEEE Computer Society Press, 409–418. 0-7695-1859-1.
[61]
J. S. Rajesh, Dean Michael Ancajas, Koushik Chakraborty, and Sanghamitra Roy. 2015. Runtime detection of a bandwidth denial attack from a rogue network-on-chip. In Proceedings of the 9th International Symposium on Networks-on-Chip. ACM, 8.
[62]
J. Sepúlveda, M. Strum, and W. J. Chau. 2010. A hybrid switching approach for NoC-based systems to avoid denial-of-service SoC attacks. In Proceedings of the 16th Iberchip Workshop (IWS’10). 23–25.
[63]
J. Sepúlveda, D. Flórez, and G. Gogniat. 2015. Efficient and flexible NoC-based group communication for secure MPSoCs. In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, Riviera Maya, Mexico, 1–6. DOI:
[64]
Jo Van Bulck, Marina Minkin, Ofir Weisse, Daniel Genkin, Baris Kasikci, Frank Piessens, Mark Silberstein, Thomas F. Wenisch, Yuval Yarom, and Raoul Strackx. 2018. Foreshadow: Extracting the keys to the intel SGX Kingdom with Transient Out-of-Order Execution. In 27th USENIX Security Symposium (USENIX Security 18). USENIX Association, Baltimore, MD, 991–1008. 978-1-939133-04-5 https://www.usenix.org/conference/usenixsecurity18/presentation/bulck.
[65]
Dmitry Evtyushkin, Ryan Riley, Nael CSE Abu-Ghazaleh, ECE, and Dmitry Ponomarev. 2018. BranchScope: A new side-channel attack on directional branch predictor. In Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems (Williamsburg, VA, USA) (seriesASPLOS’18). ACM, New York, NY, 693–707. DOI:
[66]
Moritz Lipp, Michael Schwarz, Daniel Gruss, Thomas Prescher, Werner Haas, Stefan Mangard, Paul Kocher, Daniel Genkin, Yuval Yarom, and Mike Hamburg. 2018. Meltdown. DOI:
[67]
Giorgi Maisuradze and Christian Rossow. 2018. Speculose: Analyzing the security implications of speculative execution in CPUs. CoRR abs/1801.04084 (2018), 10–30.
[68]
Marina Minkin, Daniel Moghimi, Moritz Lipp, Michael Schwarz, Jo Van Bulck, Daniel Genkin, Daniel Gruss, Berk Sunar, Frank Piessens, and Yuval Yarom. 2019. Fallout: Reading kernel writes from user space. (2019).
[69]
Koruyeh Esmaeil Mohammadian, Khasawneh Khaled N., Song Chengyu, and Abu-Ghazaleh Nael. 2018. Spectre returns! speculation attacks using the return stack buffer. In 12th USENIX Workshop on Offensive Technologies WOOT 18(seriesWOOT’18). USENIX Association, Baltimore, 10–30.
[70]
Michael Schwarz, Martin Schwarzl, Moritz Lipp, and Daniel Gruss. 2018. Netspectre: Read arbitrary memory over network. arXiv preprint arXiv:1807.10535 (2018).
[71]
Jo Van Bulck, Frank Piessens, and Raoul Strackx. 2018. Nemesis: Studying microarchitectural timing leaks in rudimentary CPU interrupt logic. In Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security (Canada) (seriesCCS’18). Association for Computing Machinery, 178–195. DOI:
[72]
Stephan van Schaik, Alyssa Milburn, Sebastian Österlund, Pietro Frigo, Giorgi Maisuradze, Kaveh Razavi, Herbert Bos, and Cristiano Giuffrida. 2019. RIDL: Rogue in-flight data load. In S&P. IEEE, CA.
[73]
Marc Andrysco, David Kohlbrenner, Keaton Mowery, Ranjit Jhala, Sorin Lerner, and Hovav Shacham. 2015. On subnormal floating point and abnormal timing. In Security and Privacy (SP), 2015 IEEE Symposium on. IEEE, San Jose, CA, 623–639.
[74]
Julian Stecklina and Thomas Prescher. 2018. LazyFP: Leaking FPU register state using microarchitectural side-channels. arXiv preprint arXiv:1806.07480 (2018).
[75]
Naomi Benger, Joop Pol, Nigel P. Smart, and Yuval Yarom. 2014. Ooh Aah... Just a Little Bit: A Small Amount of Side Channel Can Go a Long Way. In CHES. New York, NY, 75–92.
[76]
Tara Ghasempouri, Jaan Raik, Kolin Paul, Cezar Reinbrecht, Said Hamdioui, and Mottaqiallah. 2021. Verifying cache architecture vulnerabilities using a formal security verification flow. Microelectron. Reliab. 119, (2021), 114085. DOI:
[77]
Tara Ghasempouri, Jaan Raik, Kolin Paul, Cezar Reinbrecht, Said Hamdioui, and Mottaqiallah Taouil. 2020. A security verification template to assess cache architecture vulnerabilities. In 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS). 1–6. DOI:
[78]
D. Gullasch, E. Bangerter, and S. Krenn. 2011. Cache games - bringing access-based cache attacks on AES to practice. In IEEE SP. 490–505.
[79]
Gorka Irazoqui, Mehmet Sinan Inci, Thomas Eisenbarth, and Berk Sunar. 2014. Wait a Minute! A fast, Cross-VM Attack on AES. Springer International Publishing, 299–319.
[80]
F. Liu, Y. Yarom, Q. Ge, G. Heiser, and R. B. Lee. 2015. Last-level cache side-channel attacks are practical. In IEEE SP. San Jose, CA, 605–622.
[81]
Dag Arne Osvik, Adi Shamir, and Eran Tromer. 2006. Cache Attacks and countermeasures: The case of AES. In Topics in Cryptology - CT-RSA 2006. Springer, 1–20.
[82]
Ameer Shalabi, Tara Ghasempouri, Peeter Ellervee, and Jaan Raik. 2020. SCAAT: Secure Cache Alternative Address Table for mitigating cache logical side-channel attacks. In 2020 23rd Euromicro Conference on Digital System Design (DSD). IEEE, Kranj, Slovenia, 213–217. DOI:
[83]
Z. Xinjie, W. Tao, M. Dong, Z. Yuanyuan, and L. Zhaoyang. 2008. Robust first two rounds access driven Cache timing attack on AES. In CSSE, Vol. 3. Hubei, China, 785–788.
[84]
Younis A. Younis, Kashif Kifayat, Qi Shi, and Bob Askwith. 2015. A new prime and probe cache side-channel attack for cloud computing. In CSIT, 1718–1724.
[85]
Yinqian Zhang, Ari Juels, Michael K. Reiter, and Thomas Ristenpart. 2014. Cross-tenant side-channel attacks in PaaS clouds. In ACM SIGSAC. Scottsdale, Arizona, 990–1003.
[86]
B. Forlin, C. Reinbrecht, and J. Sepúlveda. 2019. Attacking real-time MPSoCs: Preemptive NoCs are vulnerable. In 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, Cuzco, Peru, 204–209.
[87]
C. Reinbrecht, B. Forlin, A. Zankl, and J. Sepú. 2018. Earthquake – A NoC-based optimized differential cache-collision attack for MPSoCs. In 2018 Design, Automation Test in Europe Conference Exhibition (DATE), 648–653. DOI:
[88]
C. Reinbrecht, A. Susin, L. Bossuet, G. Sigl, and J. Sepú. 2016. Side channel attack on NoC-based MPSoCs are practical: NoC Prime+Probe attack. In 2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI), 1–6. DOI:
[89]
Cezar Reinbrecht, Altamiro Susin, Lilian Bossuet, Georg Sigl, and Johanna Sepúlveda. 2017. Timing attack on NoC-based systems: Prime+Probe attack and NoC-based protection. Microprocess. Microsys. 52, (2017), 556–565. DOI:
[90]
J. Sepú, M. Gross, A. Zankl, and G. Sigl. 2017. Exploiting bus communication to improve cache attacks on systems-on-chips. In 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 284–289. DOI:
[91]
C. Reinbrecht, A. Susin, L. Bossuet, and J. Sepulveda. 2016. Gossip NoC - Avoiding timing side-channel attacks through traffic management. In ISVLSI 16. IEEE, Pittsburgh, 601–606.
[92]
J. Sepulveda, J. Diguet, M. Strum, and G. Gogniat. 2015. NoC-based protection for SoC time-driven attacks. Embedded Systems Letters, IEEE 7, 1 (2015), 7–10.
[93]
W. Yao and E. Suh. 2012. Efficient timing channel protection for on-chip networks. In NOCS. Lyngby, Denmark, 142–151.
[94]
CERT Coordination Center 2015. Software Engineering Institute, Carnegie Mellon University. Retrieved from https://www.sei.cmu.edu/about/divisions/cert/index.cfm.
[95]
Yefeng Ruan, Sivapriya Kalyanasundaram, and Xukai Zou. 2016. Survey of return-oriented programming defense mechanisms. Secur. Commun. Netw. 9, 10 (2016), 1247–1265.
[96]
Chair of VLSI Design, Diagnostics and Architecture. 2016. PoC - Pile of Cores. Technische Universitä. https://github.com/VLSI-EDA/PoC.
[97]
Daniel Gruss, Clémentine Maurice, Klaus Wagner, and Stefan Mangard. 2016. Flush+Flush: A fast and stealthy cache attack. In 13th International Conference on Detection of Intrusions and Malware, and Vulnerability Assessment.
[98]
Hetterich Lorenz and Schwarz Michael. 2022. Detection of intrusions and malware, and vulnerability assessment. In 19th International Conference, DIMVA, Cagliari, Italy.
[99]
Wan Junpeng, Bi Yanxiang, Zhou Zhe, and Li Zhou. 2022. MeshUp: Stateless cache side-channel attack on CPU mesh. In IEEE Symposium on Security and Privacy (SP).
[100]
Ravichandran Joseph, Na Weon Taek, Lang Jay, and Yan Mengjia. 2022. PACMAN: Attacking ARM pointer authentication with speculative execution. In IProceedings of the 49th Annual International Symposium on Computer Architecture.

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cover image ACM Computing Surveys
ACM Computing Surveys  Volume 56, Issue 2
February 2024
974 pages
EISSN:1557-7341
DOI:10.1145/3613559
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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 September 2023
Online AM: 14 June 2023
Accepted: 31 May 2023
Revised: 22 April 2023
Received: 30 June 2022
Published in CSUR Volume 56, Issue 2

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  1. Architectural attacks
  2. IP attacks
  3. functionality attacks
  4. data attacks
  5. attack model

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  • (2023)Enhancing Prime+Probe Attack Detection Using AI and Machine Learning Techniques for Improved Security2023 Global Conference on Information Technologies and Communications (GCITC)10.1109/GCITC60406.2023.10426323(1-6)Online publication date: 1-Dec-2023
  • (2023)Toward Attack Modeling Technique Addressing Resilience in Self-Driving CarIEEE Access10.1109/ACCESS.2022.323342411(2652-2673)Online publication date: 2023

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