Just Accepted
Codesign of reactor-oriented hardware and software for cyber-physical systems
Authors: 
Erling Rennemo Jellum, Martin Schoeberl, 
Edward Ashford Lee, Milica OrlandicAuthors Info & Claims
Erling Rennemo Jellum, Martin Schoeberl, Edward Ashford Lee, Milica OrlandicAuthors Info & ClaimsAccepted on 14 May 2024
Abstract
Modern cyber-physical systems often make use of heterogeneous systems-on-chip with reconfigurable logic to provide adequate computing power and flexible I/O. However, modeling, verifying, and implementing the computations spanning CPUs and reconfigurable logic is still challenging. The hardware and software components are often designed by different teams and at different levels of abstraction, making it hard to reason about the resulting computation. We propose to lift both hardware and software design to the same level of abstraction by using the Lingua Franca coordination language. Lingua Franca is based on a sparse synchronous model that allows modeling concurrency and timing while keeping a sequential model for the actual computation. We define hardware reactors as a subset of the reactor model of computation underlying Lingua Franca. We also present and evaluate reactor-chisel, a hardware runtime implementing the semantics of hardware reactors, and an extension to the Lingua Franca compiler enabling reactor-oriented hardware-software codesign.
References
[1]
[n. d.]. SYCL. https://www.khronos.org/sycl/ Accessed on July 11, 2023.
[2]
[n. d.]. Vitis Unified Software Platform Documentation: Embedded Software Development. https://docs.xilinx.com/r/en-US/ug1400-vitis-embedded Accessed on July 11, 2023.
[3]
2012. IEEE Standard for Standard SystemC Language Reference Manual. IEEE Std. 1666-20011 (2012).
[4]
Andreas Agne, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner, Marco Platzner, and Christian Plessl. 2014. ReconOS: An Operating System Approach for Reconfigurable Computing. IEEE Micro 34, 1 (2014), 60–71. https://doi.org/10.1109/MM.2013.110
[5]
Arvind, Rishiyur S. Nikhil, Daniel Rosenband, and Nirav Dave. 2004. High-Level Synthesis: An Essential Ingredient for Designing Complex ASICs. In International Conference on Computer Aided Design (ICCAD).
[6]
J. Bachrach, H. Vo, B. Richards, Y. Lee, A. Waterman, R. Avizienis, J. Wawrzynek, and K. Asanovic. 2012. Chisel: constructing hardware in a Scala embedded language. In Design Automation Conference (DAC). ACM/EDAC/IEEE, 1216–1225.
[7]
Soroush Bateni, Marten Lohstroh, Hou Seng Wong, Hokeun Kim, Shaokai Lin, Christian Menard, and Edward A. Lee. 2023. Risk and Mitigation of Nondeterminism in Distributed Cyber-Physical Systems. In Proceedings of the 21st ACM-IEEE International Conference on Formal Methods and Models for System Design (<conf-loc>, <city>Hamburg</city>, <country>Germany</country>, </conf-loc>) (MEMOCODE ’23). Association for Computing Machinery, New York, NY, USA, 1–11. https://doi.org/10.1145/3610579.3613219
[8]
Soroush Bateni, Marten Lohstroh, Hou Seng Wong, Rohan Tabish, Hokeun Kim, Shaokai Lin, Christian Menard, Cong Liu, and Edward A Lee. 2022. Xronos: Predictable coordination for safety-critical distributed embedded systems. arXiv preprint arXiv:2207.09555 (2022).
[9]
Albert Benveniste and Gérard Berry. 1991. The Synchronous Approach to Reactive and Real-Time Systems. Proc. IEEE 79, 9 (1991), 1270–1282.
[10]
Gérard Berry and Georges Gonthier. 1992. The Esterel synchronous programming language: Design, semantics, implementation. Science of Computer Programming 19, 2 (1992), 87–152. http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.17.5606
[11]
Dominique Blouin, Gilberto Ochoa-Ruiz, Yvan Eustache, and Jean-Philippe Diguet. 2015. Kaolin: A system-level AADL tool for FPGA design reuse, upgrade and migration. In 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS). 1–8. https://doi.org/10.1109/AHS.2015.7231166
[12]
Etienne Borde, Smail Rahmoun, Fabien Cadoret, Laurent Pautet, Frank Singhoff, and Pierre Dissaux. 2014. Architecture models refinement for fine grain timing analysis of embedded systems. In 2014 25nd IEEE International Symposium on Rapid System Prototyping. 44–50. https://doi.org/10.1109/RSP.2014.6966691
[13]
Jeronimo Castrillon, Karol Desnos, Andrés Goens, and Christian Menard. 2022. Dataflow Models of Computation for Programming Heterogeneous Multicores. Springer Nature Singapore, Singapore, 1–40. https://doi.org/10.1007/978-981-15-6401-7_45-2
[14]
Jack B. Dennis. 1974. First Version Data Flow Procedure Language. Report MAC TM61. MIT Laboratory for Computer Science.
[15]
S.A. Edwards. 2006. The Challenges of Synthesizing Hardware from C-Like Languages. IEEE Design & Test of Computers 23, 5 (2006), 375–386. https://doi.org/10.1109/MDT.2006.134
[16]
Kermin Fleming and Michael Adler. 2016. The LEAP FPGA operating system. FPGAs for software programmers (2016), 245–258.
[17]
Håvard Grip. [n. d.]. Suviving an In-Flight Anomaly: What Happened on Ingenuity’s Sixth Flight. NASA Mars Helicopter Blog ([n. d.]). https://mars.nasa.gov/technology/helicopter/status/305/surviving-an-in-flight-anomaly-what-happened-on-ingenuitys-sixth-flight/
[18]
C. A. R. Hoare. 1978. Communicating Sequential Processes. Commun. ACM 21, 8 (1978), 666–677.
[19]
Axel Jantsch. 2003. Modeling Embedded Systems and SoCs - Concurrency and Time in Models of Computation. Morgan Kaufmann.
[20]
Axel Jantsch and Ingo Sander. 2005. Models of computation and languages for embedded system design. Computers and Digital Techniques, IEE Proceedings - 152 (04 2005), 114 – 129. https://doi.org/10.1049/ip-cdt:20045098
[21]
Erling R. Jellum, Torleiv H. Bryne, Tor Arne Johansen, and Milica Orlandic. 2022. The Syncline Model - Analyzing the Impact of Time Synchronization in Sensor Fusion. In 2022 IEEE Conference on Control Technology and Applications (CCTA). 1446–1453. https://doi.org/10.1109/CCTA49430.2022.9966179
[22]
Erling R. Jellum, Shaokai Lin, Peter Donovan, Chadlia Jerad, Edward Wang, Marten Lohstroh, Edward A. Lee, and Martin Schoeberl. 2023. InterPRET: A Time-Predictable Multicore Processor. In Proceedings of Cyber-Physical Systems and Internet of Things Week 2023 (San Antonio, TX, USA) (CPS-IoT Week ’23). Association for Computing Machinery, New York, NY, USA, 331–336. https://doi.org/10.1145/3576914.3587497
[23]
Erling Rennemo Jellum, Shaokai Lin, Peter Donovan, Efsane Soyer, Fuzail Shakir, Torleiv Bryne, Milica Orlandic, Marten Lohstroh, and Edward A. Lee. 2023. Beyond the Threaded Programming Model on Real-Time Operating Systems. In Fourth Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2023) (Open Access Series in Informatics (OASIcs), Vol. 108), Federico Terraneo and Daniele Cattaneo (Eds.). Schloss Dagstuhl – Leibniz-Zentrum für Informatik, Dagstuhl, Germany, 3:1–3:13. https://doi.org/10.4230/OASIcs.NG-RES.2023.3
[24]
Erling Rennemo Jellum, Yaman Umuruglu, Milica Orlandic, and Martin Schoeberl. 2023. FPGA-tidbits: Rapid Prototyping of FPGA Accelerators in Chisel. In 2023 26th Euromicro Conference on Digital System Design (DSD). 153–160. https://doi.org/10.1109/DSD60849.2023.00031
[25]
Gilles Kahn. 1974. The Semantics of a Simple Language for Parallel Programming. In Proc. of the IFIP Congress 74. North-Holland Publishing Co., 471–475.
[26]
Myron Decker King et al. 2013. A methodology for hardware-software codesign. Ph. D. Dissertation. Massachusetts Institute of Technology.
[27]
Kaushal Kumar, Ritesh Kumar Mishra, and Durgesh Nandan. 2020. Efficient Hardware of RGB to Gray Conversion Realized on FPGA and ASIC. Procedia Computer Science 171 (2020), 2008–2015. https://doi.org/10.1016/j.procs.2020.04.215 Third International Conference on Computing and Network Communications (CoCoNet’19).
[28]
Edward A. Lee. 2006. The Problem with Threads. Computer 39, 5 (2006), 33–42. https://doi.org/10.1109/MC.2006.180
[29]
Edward A. Lee. 2009. Computing Needs Time. Commun. ACM 52, 5 (2009), 70–79. https://doi.org/10.1145/1506409.1506426
[30]
E. A. Lee and D. G. Messerschmitt. 1987. Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing. IEEE Trans. Comput. C-36, 1 (1987), 24–35. https://doi.org/10.1109/TC.1987.5009446
[31]
E. A. Lee and D. G. Messerschmitt. 1987. Synchronous Data Flow. Proc. IEEE 75, 9 (1987), 1235–1245. https://doi.org/10.1109/PROC.1987.13876
[32]
Edward A. Lee and Alberto Sangiovanni-Vincentelli. 1998. A Framework for Comparing Models of Computation. IEEE Transactions on Computer-Aided Design of Circuits and Systems 17, 12 (1998), 1217–1229. http://ptolemy.eecs.berkeley.edu/publications/papers/98/framework/
[33]
Christian Lienen, Marco Platzner, and Bernhard Rinner. 2020. ReconROS: Flexible Hardware Acceleration for ROS2 Applications. In 2020 International Conference on Field-Programmable Technology (ICFPT). 268–276. https://doi.org/10.1109/ICFPT51103.2020.00046
[34]
Marten Lohstroh. 2020. Reactors: A Deterministic Model of Concurrent Computation for Reactive Systems. Ph. D. Dissertation. EECS Department, University of California, Berkeley. http://www2.eecs.berkeley.edu/Pubs/TechRpts/2020/EECS-2020-235.html
[35]
Marten Lohstroh, Edward Lee, Soroush Bateni, Christian Menard, Peter Donovan, Clément Fournier, Hou Seng (Steven) Wong, Alexander Schulz-Rosengarten, Erling Rennemo Jellum, Hokeun Kim, Matt Weber, Shaokai Lin, and Anirudh Rengarajan. [n. d.]. Lingua Franca. https://github.com/lf-lang/lingua-franca
[36]
Marten Lohstroh, Christian Menard, Soroush Bateni, and Edward A. Lee. 2021. Toward a Lingua Franca for Deterministic Concurrent Systems. ACM Transactions on Embedded Computing Systems (TECS), Special Issue on FDL’19 20, 4 (May 2021), Article 36. https://doi.org/10.1145/3448128
[37]
Marten Lohstroh, Íñigo Íncer Romeo, Andrés Goens, Patricia Derler, Jeronimo Castrillon, Edward A. Lee, and Alberto Sangiovanni-Vincentelli. 2020. Reactors: A Deterministic Model for Composable Reactive Systems. In Cyber Physical Systems. Model-Based Design, Roger Chamberlain, Martin Edin Grimheden, and Walid Taha (Eds.). Springer International Publishing, Cham, 59–85.
[38]
Marten Lohstroh, Martin Schoeberl, Andrés Goens, Armin Wasicek, Christopher Gill, Marjan Sirjani, and Edward A. Lee. 2019. Actors Revisited for Time-Critical Systems. In Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019. 152:1–152:4.
[39]
Christian Menard, Marten Lohstroh, Soroush Bateni, Matthew Chorlian, Arthur Deng, Peter Donovan, Clément Fournier, Shaokai Lin, Felix Suchert, Tassilo Tanneberger, Hokeun Kim, Jeronimo Castrillon, and Edward A. Lee. 2023. High-Performance Deterministic Concurrency Using Lingua Franca. ACM Trans. Archit. Code Optim. (aug 2023). https://doi.org/10.1145/3617687 Just Accepted.
[40]
Aaftab Munshi. 2009. The opencl specification. In 2009 IEEE Hot Chips 21 Symposium (HCS). IEEE, 1–314.
[41]
Ingo Sander. 2003. System Modeling and Design Refinement in ForSyDe. Thesis.
[42]
Alexander Schulz-Rosengarten, Reinhard von Hanxleden, Marten Lohstroh, Edward A Lee, and Soroush Bateni. 2023. Polyglot Modal Models through Lingua Franca. In Proceedings of Cyber-Physical Systems and Internet of Things Week 2023. 337–342.
[43]
Todor Stefanov, Claudiu Zissulescu, Alexandru Turjan, Bart Kienhuis, and Ed F. Deprettere. 2004. System design using Khan process networks: the Compaan/Laura approach. Proceedings Design, Automation and Test in Europe Conference and Exhibition 1 (2004), 340–345 Vol.1.
[44]
Wikipedia. 2023. Round-trip engineering — Wikipedia, The Free Encyclopedia. http://en.wikipedia.org/w/index.php?title=Round-trip%20engineering&oldid=1172040452. [Online; accessed 19-September-2023].
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- Codesign of reactor-oriented hardware and software for cyber-physical systems
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Publication History
Online AM: 12 June 2024
Accepted: 14 May 2024
Revised: 15 April 2024
Received: 22 September 2023
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