Article

An exact algorithm for coupling-free routing

Authors:

Ryan Kastner,

Elaheh Bozorgzadeh,

Majid SarrafzadehAuthors Info & Claims

ISPD '01: Proceedings of the 2001 international symposium on Physical design

Pages 10 - 15

https://doi.org/10.1145/369691.369711

Published: 01 April 2001 Publication History

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Abstract

In this wrok, we develop methods to reduce interconnect delay and noise caused by coupling. First, we explain the Coupling-Free Routing (CFR) problem. CFR takes a set of nets and tries to find a one-bend couple-free routing for a subset of nets. A routed net must not couple with any other routed net. We define coupling as a boolean variable which is true when the coupling of two nets is greater than some threshold. Any pair-wise coupling definition can be used. We argue that this problem is useful in both global and detailed routing

We develop an exact algorithm for the CFR decision problem via a transformation to 2-satisfiability. This algorithm runs in linear time. The decision problem determines whether the given set of nets is coupling-free routable. Next, we present the implication graph which models the dependencies associated with CFR. Also, we look at some of the properties associated with the graph.

Finally, we develop a new algorithm for the Maximum Coupling-Free Layout (MAX-CFL) problem. Given a set of nets, the MAX-CFL is defined as finding a subset of nets that are coupling-free routable. The subset should have maximum size and/or critically. The new algorithm, called implication algorithm, uses properties assoicated with the implication graph and experiments show that it consistently finds the best solution in terms of number of nets routed as compared to previous algorithms

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An exact algorithm for coupling-free routing

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Published In

ISPD '01: Proceedings of the 2001 international symposium on Physical design

April 2001

245 pages

ISBN:1581133472

DOI:10.1145/369691

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 01 April 2001

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ISPD01: International Symposium on Physical Design

April 1 - 4, 2001

California, Sonoma, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

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Li YLin SNishizawa SSu HFong MChen OOnodera H(2022)NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid MapIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.316733941:12(5568-5581)Online publication date: Dec-2022
https://doi.org/10.1109/TCAD.2022.3167339
Hsu CLin MChang Y(2015)Crosstalk-aware multi-bit flip-flop generation for power optimizationIntegration, the VLSI Journal10.1016/j.vlsi.2014.08.00248:C(146-157)Online publication date: 1-Jan-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2014.08.002
Mukherjee SPatra JRoy S(2013)Congestion Balancing Global RouterVLSI Design and Test10.1007/978-3-642-42024-5_27(223-232)Online publication date: 2013
https://doi.org/10.1007/978-3-642-42024-5_27
Hsu CChang YLin M(2012)Crosstalk-aware power optimization with multi-bit flip-flops17th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2012.6164987(431-436)Online publication date: Jan-2012
https://doi.org/10.1109/ASPDAC.2012.6164987
Su PHuang HHsieh T(2011)Timing- and interference-free multi-layer routing tree2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2011.6026579(1-4)Online publication date: Aug-2011
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Behjat LChiang ARakai LJianhua Li (2008)An effective congestion-based integer programming model for VLSI global routing2008 Canadian Conference on Electrical and Computer Engineering10.1109/CCECE.2008.4564673(000931-000936)Online publication date: May-2008
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