Article

Analysis and optimization of thermal issues in high-performance VLSI

Authors:

Kaustav Banerjee,

Massoud Pedram,

Amir H. AjamiAuthors Info & Claims

ISPD '01: Proceedings of the 2001 international symposium on Physical design

Pages 230 - 237

https://doi.org/10.1145/369691.369779

Published: 01 April 2001 Publication History

Abstract

This paper provides an overview of various thermal issues in high-performance VLSI with especial attention to their implications for performance and reliability. More specifically, it examines the impact of thermal effects on both interconnect design and electromigration reliability and discusses their impact on the allowable current density limits. Furthermore, it also discusses how thermal and reliability constrained current density limits may conflict with those obtained through purely performance based criterion. Additionally, it is shown that chip level thermal effects can have a significant impact on large-scale circuit optimization techniques, including the clock-skew minimization scheme, and can influence other physical design problem formulations. Finally, high-current interconnect design rules for ESD and I/O circuits are also examined.

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Cited By

Saligram RDatta SRaychowdhury A(2022)Design Space Exploration of Interconnect Materials for Cryogenic Operation: Electrical and Thermal AnalysesIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.319563669:11(4610-4618)Online publication date: Nov-2022
https://doi.org/10.1109/TCSI.2022.3195636
Oh DChoi MKim J(2019)Thermal-aware 3D Symmetrical Buffered Clock Tree SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/331379824:3(1-22)Online publication date: 5-Apr-2019
https://dl.acm.org/doi/10.1145/3313798
Sultan HChauhan ASarangi S(2019)A Survey of Chip-level Thermal SimulatorsACM Computing Surveys10.1145/330954452:2(1-35)Online publication date: 30-Apr-2019
https://dl.acm.org/doi/10.1145/3309544
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Index Terms

Analysis and optimization of thermal issues in high-performance VLSI
1. Hardware
  1. Integrated circuits
    1. Logic circuits
  2. Very large scale integration design

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cover image ACM Conferences

ISPD '01: Proceedings of the 2001 international symposium on Physical design

April 2001

245 pages

ISBN:1581133472

DOI:10.1145/369691

Copyright © 2001 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 April 2001

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Cited By

Saligram RDatta SRaychowdhury A(2022)Design Space Exploration of Interconnect Materials for Cryogenic Operation: Electrical and Thermal AnalysesIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.319563669:11(4610-4618)Online publication date: Nov-2022
https://doi.org/10.1109/TCSI.2022.3195636
Oh DChoi MKim J(2019)Thermal-aware 3D Symmetrical Buffered Clock Tree SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/331379824:3(1-22)Online publication date: 5-Apr-2019
https://dl.acm.org/doi/10.1145/3313798
Sultan HChauhan ASarangi S(2019)A Survey of Chip-level Thermal SimulatorsACM Computing Surveys10.1145/330954452:2(1-35)Online publication date: 30-Apr-2019
https://dl.acm.org/doi/10.1145/3309544
Wang DWang WJin Y(2019)A Complex Integrated Circuit Structure Transformation, Modeling and Simulation Method2019 IEEE 69th Electronic Components and Technology Conference (ECTC)10.1109/ECTC.2019.00309(2016-2021)Online publication date: May-2019
https://doi.org/10.1109/ECTC.2019.00309
Petrosyants KRyabov NBatarueva E(2018)Compact SPICE Models of the Standard Layout Fragments in LSI Interconnections2018 IEEE East-West Design & Test Symposium (EWDTS)10.1109/EWDTS.2018.8524730(1-5)Online publication date: Sep-2018
https://doi.org/10.1109/EWDTS.2018.8524730
Alrashidi A(2016)Numerical Study of Conjugate Heat Transfer for Cooling the Circuit BoardJournal of Electronics Cooling and Thermal Control10.4236/jectc.2016.6301106:03(120-126)Online publication date: 2016
https://doi.org/10.4236/jectc.2016.63011
Wang NJin YPi YWang W(2016)A full chip scale numerical simulation method for thermal management of 3D IC2016 17th International Conference on Electronic Packaging Technology (ICEPT)10.1109/ICEPT.2016.7583226(690-693)Online publication date: Aug-2016
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LIMA ABARROS CSILVEIRA LXAVIER-DE-SOUZA SVALDERRAMA C(2014)Parallel Cyclostationarity-Exploiting Algorithm for Energy-Efficient Spectrum SensingIEICE Transactions on Communications10.1587/transcom.E97.B.326E97.B:2(326-333)Online publication date: 2014
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Wu PHo T(2013)Bus-driven floorplanning with thermal considerationIntegration, the VLSI Journal10.1016/j.vlsi.2012.11.00246:4(369-381)Online publication date: 1-Sep-2013
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Wu PHo TChang NNakamura HInoue KOsada KPoncino M(2011)Thermal-aware bus-driven floorplanningProceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design10.5555/2016802.2016852(205-210)Online publication date: 1-Aug-2011
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