Article

Modeling and forecasting of manufacturing variations (embedded tutorial)

Author:

Sani R. NassifAuthors Info & Claims

ASP-DAC '01: Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Pages 145 - 150

https://doi.org/10.1145/370155.370308

Published: 30 January 2001 Publication History

Abstract

Process-induced variations are an important consideration in the design of integrated circuits. Until recently, it was sufficient to model die-to-die shifts in device performance, leading to the well known worst-case modeling and design methodology [1, 2]. However, current and near-future in-tegrated circuits are large enough that device and intercon-nect parameter variations within the chip are as important as those same variations from chip to chip. This presents a new set of challenges for process modeling and characterization and for the associated design tools and method-ologies. This paper examines the sources and trends of process variability, the new challenges associated with the increase in within-die variability analysis, and proposes a modeling and simulation methodology to deal with this variability.

References

[1]

S. W. Director and W. Maly, editors. Statistical Approach to VLSI, volume 8 of Advances in CAD for VLSI.North- Holland, 1994.

[2]

J. Power, B. Donnellan, A. Mathewson, and W. Lane. Relating statistical mosfet model parameter variabilities to ic manufacturing process fluctuations enabling realistic worst case design. IEEE Trans. Semiconductor Manufacturing, Aug 1994.

[3]

A. Misaka, A. Goda, K. Matsuoka, H. Umimoto, and S. Odanaka. A statistical critical dimension control at cmos cell level. In Proceedings of IEDM, 1996.

[4]

S. R. Nassif. Within-chip variability analysis. In Proceedings of IEDM, 1998.

[5]

M. Eisele, J. Berthold, D. Schmitt-Landseidel, and R. Mahnkopf. The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. IEEE Trans. VLSI, Dec 1997.

Digital Library

[6]

The National Technology Roadmap for Semiconductors, 1997.

[7]

C. Alpert, A. Devghan, and S. Quay. Buffer insertion with accurate models for gate and interconnect delay. In Proceedings of DAC, 1999.

Digital Library

[8]

M. McKay, R. Beckman, and W. Conover. A comparison of three methods fos selecting values for input variables in the analysis of output from computer codes. Technometrics, May 1979.

[9]

L. W. Nagel. SPICE2: A Computer Program to Simulate Semiconductor Circuits. PhD thesis, University of California, Berkeley, 1975.

[10]

Y. Cheng, M. Chan, K. hui, M. Jeng, Z. Liu, J. Huang, K. Chen, J. Chen, R. Tu, P. Kp, and C. Hu. BSIM3v3 Manual. EECS Dept, Berkeley, 1996.

[11]

C. Michael and M. Ismail. Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits.Kluwer, 1993.

Digital Library

[12]

A. Dharchoudhury et. al. Design and analysis of power distribution networks in powerpc TM microprocessors. In Proceedings of DAC, 1998.

Digital Library

[13]

M. K. Gowan, L. L. Biro, and D. B. Jackson. Power considerations in the design of the alpha 21264 microprocessor. In Proceedings of DAC, 1998.

Digital Library

[14]

G. Steele et. al. Full-chip verification methods for dsm power distribution systems. In Proceedings of DAC, 1998.

Digital Library

[15]

Y. M. Jiang and K. T. Cheng. Analysis of performance impact caused by power supply noise in deep submicron devices. In Proceedings of DAC, 1999.

Digital Library

[16]

S. Nassif and J. Kozhata. Fast power grid simulation. In Proceedings of DAC, 2000.

Digital Library

[17]

G. Digele, S. Lindenkreuz, and E. Kasper. Fully coupled dynamic electro-thermal simulation. IEEE Trans. VLSI, Sep 1997.

Digital Library

[18]

V. Szekely, A. Poppe, A. Pahi, A. Csendes, G. Hajas, and M. Rencz. Electro-thermal and logi-thermal simulation of vlsi designs. IEEE Trans. VLSI, Sep 1997.

Digital Library

[19]

B. E. Stine, D. S. Boning, and J. E. Chung. Analysis and decomposition of spatial variation in integrated circuit processes and devices. IEEE Trans. Semiconductor Manufacturing, Feb 1997.

[20]

C. Yu, T. Maung, C. Spanos, D. Boning, J. Chung, H. Liu, K. Chang, and D. Bertelink. Use of short-loop electrical measurements for yield improvement. IEEE Trans. Semiconductor manufacturing, May 1995.

Cited By

Shang CCao JZhu TZhang YNiu BLi H(2024)CADFA: A Clock Skew-Based Active Device Fingerprint Authentication Scheme for Class-1 IoT DevicesIEEE Systems Journal10.1109/JSYST.2024.335122218:1(590-599)Online publication date: Mar-2024
https://doi.org/10.1109/JSYST.2024.3351222
Rita MAru SManish B(2020)Timing analysis journey from OCV to LVFJournal of Physics: Conference Series10.1088/1742-6596/1706/1/0120811706(012081)Online publication date: 22-Dec-2020
https://doi.org/10.1088/1742-6596/1706/1/012081
Balasubramanian PMaskell DNaayagi RMastorakis N(2019)Early Output Quasi-Delay-Insensitive Array MultipliersElectronics10.3390/electronics80404448:4(444)Online publication date: 18-Apr-2019
https://doi.org/10.3390/electronics8040444
Show More Cited By

Index Terms

Modeling and forecasting of manufacturing variations (embedded tutorial)
1. Applied computing
  1. Physical sciences and engineering
    1. Electronics
2. Hardware
  1. Integrated circuits
  2. Robustness

Recommendations

Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits
VTS '03: Proceedings of the 21st IEEE VLSI Test Symposium

The ITRS (International Technology Roadmap forSemiconductors) predicts aggressive scaling down of devicesize, transistor threshold voltage and oxide thickness to meetgrowing demands for performance. Such scaling will resultin an exponential increase in ...
Embedded Tutorial: Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies
VLSID '06: Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design

MOS Transistors with sub 100 nm channel lengths need a gate oxide thickness in the range of 1 - 2 nm to combat the short channel effects. However at these gate dielectric thicknesses, the gate current is no longer negligible. In this paper, we report ...
McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations
As technology has moved into the deep-submicrometer regime, the shrinking feature size has placed a considerable stress on CMOS fabrication due to short-channel effects (SCEs) and excessive leakage. Although many research efforts have been devoted to ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ASP-DAC '01: Proceedings of the 2001 Asia and South Pacific Design Automation Conference

January 2001

662 pages

ISBN:0780366344

DOI:10.1145/370155

Chairman:
Satoshi Goto
NEC Corp., Kawasaki, Japan

Copyright © 2001 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

IEICE: Inst of Electronics, Info & Communication Engineers
IPSJ: Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
IEEE HK CAS: IEEE HK CAS and Comm. Joint Chapter

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 January 2001

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ASP-DAC01

Sponsor:

IEICE
IPSJ
SIGDA
IEEE HK CAS

ASP-DAC01: Asia and South Pacific Design Automation Conference 2001

Yokohama, Japan

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Upcoming Conference

ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

41
Total Citations
View Citations
471
Total Downloads

Downloads (Last 12 months)6
Downloads (Last 6 weeks)0

Reflects downloads up to 13 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Shang CCao JZhu TZhang YNiu BLi H(2024)CADFA: A Clock Skew-Based Active Device Fingerprint Authentication Scheme for Class-1 IoT DevicesIEEE Systems Journal10.1109/JSYST.2024.335122218:1(590-599)Online publication date: Mar-2024
https://doi.org/10.1109/JSYST.2024.3351222
Rita MAru SManish B(2020)Timing analysis journey from OCV to LVFJournal of Physics: Conference Series10.1088/1742-6596/1706/1/0120811706(012081)Online publication date: 22-Dec-2020
https://doi.org/10.1088/1742-6596/1706/1/012081
Balasubramanian PMaskell DNaayagi RMastorakis N(2019)Early Output Quasi-Delay-Insensitive Array MultipliersElectronics10.3390/electronics80404448:4(444)Online publication date: 18-Apr-2019
https://doi.org/10.3390/electronics8040444
Balasubramanian PMaskell DMastorakis N(2018)Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry LogicElectronics10.3390/electronics71002437:10(243)Online publication date: 9-Oct-2018
https://doi.org/10.3390/electronics7100243
Xu YYang JMelhem R(2018)A Process-Variation-Tolerant Method for Nanophotonic On-Chip NetworkACM Journal on Emerging Technologies in Computing Systems10.1145/320807314:2(1-23)Online publication date: 11-Jul-2018
https://dl.acm.org/doi/10.1145/3208073
Guthaus M(2016)Clock Design and SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-13(261-282)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-13
Bhatnagar PKumar NBhatnagar PAgarwal N(2016)Logic depth aware context independent timing model generation10.1063/1.4942704(020022)Online publication date: 2016
https://doi.org/10.1063/1.4942704
Kumar NBhatnagar PAgarwal NBhatnagar P(2016)Challenges in probabilistic timing model generation in integrated circuits10.1063/1.4942690(020008)Online publication date: 2016
https://doi.org/10.1063/1.4942690
Xu YYang JMelhem RNapoli CSalapura VFranke HHou R(2015)BandArbProceedings of the 12th ACM International Conference on Computing Frontiers10.1145/2742854.2742876(1-8)Online publication date: 6-May-2015
https://dl.acm.org/doi/10.1145/2742854.2742876
He WHerrmann APimentel AWong SPelosi GKoren IAgosta GBarenghi A(2015)Placement Security Analysis for Side-Channel Resistant Dual-Rail Scheme in FPGAProceedings of the Second Workshop on Cryptography and Security in Computing Systems10.1145/2694805.2694813(39-42)Online publication date: 19-Jan-2015
https://dl.acm.org/doi/10.1145/2694805.2694813
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents