Article

On-chip communication architecture for OC-768 network processors

Authors:

Faraydon Karim,

Ramesh RaoAuthors Info & Claims

DAC '01: Proceedings of the 38th annual Design Automation Conference

Pages 678 - 683

https://doi.org/10.1145/378239.379047

Published: 22 June 2001 Publication History

Abstract

The need for network processors capable of forwarding IP packets at OC-192 and higher data rates has been well established. At the same time, there is a growing need for complex tasks, like packet classification and differentiated services, to be performed by network processors. At OC-768 data rate, a network processor has 9 nanoseconds to process a minimum-size IP packet. Such ultra high-speed processing, involving complex memory-intensive tasks, can only be achieved by multi-CPU distributed memory systems, using very high performance on-chip communication architectures. In this paper, we propose a novel communication network architecture for 8-CPU distributed-memory systems that has the potential to deliver the throughput required in next generation routers. We then show that our communication architecture can easily scale to accommodate much greater number of network nodes. Our network architecture yields higher performance than the traditional bus and crossbar yet has low implementation cost. It is quite flexible and can be implemented in either packet or circuit switched mode. We will compare and contrast our proposed architecture with busses and crossbars using metrics such as throughput and physical layout cost.

References

[1]

Kumar, V.P.; Lakshman, T.V.; Stiliadis, D., "Beyond best effort: router architectures for the differentiated services of tomorrow's Internet," IEEE Communications Magazine, Volume: 36 Issue: 5, May 1998, pp. 152 - 164.

Digital Library

[2]

F. Karim, "Network Processors: The New Frontier in SoC Design and Validation," Presentation, DATE conference, 2000.

[3]

Lakshman, T.V.; Stiliadis, D.; "High-Speed Policybased Packet Forwarding Using Efficient Multidimensional Range Matching," Proceedings of ACM SIGCOMM, Sept. 1998, pp. 191-202.

Digital Library

[4]

K.Lahiri, A.Raghunathan, S.Dey, "Fast performance analysis of bus-based system-on-chip communication architectures", in Proc. Intl Conf. on Computer Aided Design, pp. 566-572, Nov. 1997.

Digital Library

[5]

K.Lahiri, A.Raghunathan, S.Dey, "Performance analysis of systems with multi-channel communication architectures", in Proc. Int. Conf. VLSI Design, pp. 530- 537, Jan. 2000.

Digital Library

[6]

K.Lahiri, A.Raghunathan, S.Dey, "Evaluation of the traffic performance characteristics of system-on-chip communication architectures", in Proc. Int. Conf. VLSI Design, pp. 29-35, Jan. 2001.

Digital Library

[7]

T.Yen and W.Wolf, "Communication synthesis for distributed embedded systems", in Proc. Intl Conf. on Computer Aided Design, pp. 288-294, Nov. 1995.

Digital Library

[8]

J.Daveau, T.B.Ismail, A.A.Jerraya,"Synthesis of system-level communication by an allocation based approach", in Proc. Int. Symp. On System Level Synthesis, pp. 150-155, Sept. 1995.

Digital Library

[9]

J.A.Rowson and A.Sangiovanni-Vincentelli, "Interface based design", in Proc. Design Automation Conf. pp. 178-183, Jun. 1997.

Digital Library

[10]

R.B.Ortega and G.Borriello, "Communication synthesis for distributed embedded systems", in Proc. Intl Conf. on Computer Aided Design, pp. 437-444, Nov. 1998.

Digital Library

[11]

M.Gasteier and M.Glesner,"Bus-based communication synthesis on system level", ACM Trans. Design Automation Electronic Systems, pp. 1-11, Jan. 1999.

Digital Library

[12]

K.Lahiri, A.Raghunathan, G.Lakhshminarayana, S.Dey, "Communication Architecture Tuners: a methodology for the design of high performance communication architectures for system-on-chips", in Proc. Design Automation Conf. pp. 513-518, Jun. 2000.

Digital Library

[13]

K.Lahiri, A.Raghunathan, S.Dey, "Efficient Exploration of the SoC Communication Architecture Design Space", in Proc. Intl Conf. on Computer Aided Design, pp. 424- 430, Nov. 2000.

Digital Library

[14]

"IBM On-chip CoreConnect Bus Architecture", http://www.chips.ibm.com/products/coreconnect/index.h tml

[15]

"Peripheral Interconnect Bus Architecture", http://www.omimo.be

[16]

"Sonics Integration Architecture, Sonics Inc", http://www.sonicsinc.com

[17]

B. Cordan, "An efficient bus architecture for system-on-achip design", Proc. Custom Integrated Circuits Conf., pp. 623-626, 1999.

[18]

D.Flynn, "AMBA: enabling reusable on-chip designs", IEEE Micro, pp. 20-27, vol 7, no. 4, 1997.

Digital Library

[19]

"On chip bus attributes specification 1 OCB 1 1.0, Onchip bus DWG", http://www.vsi.org/library/specs/summary.htm

[20]

Chen, J. and Stern, T., "Throughput Analysis, Optimal Buffer Allocation, and Traffic Imbalance Study of a Generic Nonblocking Packet Switch, IEEE JSAC, Vol. 9, No. 3, 1991, pp. 439-449.

Digital Library

[21]

Cinlar, E., Introduction to Stochastic Processes, pp. 87- 88, Prentice Hall, 1975.

[22]

Gross, D., and Harris, C., Fundamental of Queueing Theory, pp. 297-300, John Wiley & Sons, 3rd Edition, 1998.

Digital Library

[23]

Gross, D., and Harris, C., Fundamental of Queueing Theory, pp. 61-68, John Wiley & Sons, 3rd Edition, 1998.

Digital Library

Cited By

De Liz Bomer RZeferino CSeman LLeithardt V(2023)Worst-Case Communication Time Analysis for On-Chip Networks With Finite BuffersIEEE Access10.1109/ACCESS.2023.325551611(25120-25131)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3255516
Yadav AMrityunjay Singh KBiswas S(2020)Adaptive BFS Based Fault Tolerant Routing Algorithm for Network on Chip2020 IEEE REGION 10 CONFERENCE (TENCON)10.1109/TENCON50793.2020.9293760(170-175)Online publication date: 16-Nov-2020
https://doi.org/10.1109/TENCON50793.2020.9293760
Nongpoh BRay RDas MBanerjee A(2019)Enhancing Speculative Execution With Selective Approximate ComputingACM Transactions on Design Automation of Electronic Systems10.1145/330765124:2(1-29)Online publication date: 14-Feb-2019
https://dl.acm.org/doi/10.1145/3307651
Show More Cited By

Index Terms

On-chip communication architecture for OC-768 network processors

Recommendations

On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches

Traditionally, design-space exploration for systems-on-chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, a shift from ...
Off-chip communication architectures for high throughput network processors

In this paper, we propose a new interconnection mechanism for network line cards. We project that the packet storage needs for the next-generation networks will be much higher. Such that the number of memory modules required to store the packets will be ...
Core Network Interface Architecture and Latency Constrained On-Chip Communication
ISQED '06: Proceedings of the 7th International Symposium on Quality Electronic Design

This paper proposes a Core Network Interface (CNI) architecture to interface IP cores with on-chip networks. Besides the basic functionality of packetizing communication requests and responses, we expect the CNI to provide additional services critical ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '01: Proceedings of the 38th annual Design Automation Conference

June 2001

863 pages

ISBN:1581132972

DOI:10.1145/378239

Chairman:
Jan Rabaey
Univ. of California

Copyright © 2001 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 June 2001

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DAC01

Sponsor:

EDAC
SIGDA
IEEE-CAS

DAC01: 38th ACM/IEEE-CAS/ EDAC Design Automation Conference

Nevada, Las Vegas, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

92
Total Citations
View Citations
44
Total Downloads

Downloads (Last 12 months)4
Downloads (Last 6 weeks)1

Reflects downloads up to 10 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

De Liz Bomer RZeferino CSeman LLeithardt V(2023)Worst-Case Communication Time Analysis for On-Chip Networks With Finite BuffersIEEE Access10.1109/ACCESS.2023.325551611(25120-25131)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3255516
Yadav AMrityunjay Singh KBiswas S(2020)Adaptive BFS Based Fault Tolerant Routing Algorithm for Network on Chip2020 IEEE REGION 10 CONFERENCE (TENCON)10.1109/TENCON50793.2020.9293760(170-175)Online publication date: 16-Nov-2020
https://doi.org/10.1109/TENCON50793.2020.9293760
Nongpoh BRay RDas MBanerjee A(2019)Enhancing Speculative Execution With Selective Approximate ComputingACM Transactions on Design Automation of Electronic Systems10.1145/330765124:2(1-29)Online publication date: 14-Feb-2019
https://dl.acm.org/doi/10.1145/3307651
Li TWang QZhu YJiang JHe GJin JMao ZJing N(2019)A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add OperationsACM Transactions on Design Automation of Electronic Systems10.1145/330649524:2(1-22)Online publication date: 21-Mar-2019
https://dl.acm.org/doi/10.1145/3306495
Pomeranz I(2019)Incomplete Tests for Undetectable Faults to Improve Test Set QualityACM Transactions on Design Automation of Electronic Systems10.1145/330649324:2(1-13)Online publication date: 13-Feb-2019
https://dl.acm.org/doi/10.1145/3306493
Gupta AHuang JYamashita SRoy S(2019)Design Automation for Dilution of a Fluid Using Programmable Microfluidic Device--Based BiochipsACM Transactions on Design Automation of Electronic Systems10.1145/330649224:2(1-24)Online publication date: 27-Feb-2019
https://dl.acm.org/doi/10.1145/3306492
Jung JNam GChung WShin Y(2019)Integrated Latch Placement and Cloning for Timing OptimizationACM Transactions on Design Automation of Electronic Systems10.1145/330161324:2(1-17)Online publication date: 9-Feb-2019
https://dl.acm.org/doi/10.1145/3301613
Bhowmik BDeka JBiswas SBhattacharya B(2019)Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-ChipACM Transactions on Design Automation of Electronic Systems10.1145/329153224:2(1-29)Online publication date: 10-Jan-2019
https://dl.acm.org/doi/10.1145/3291532
Luo HLiu QHu JLi QShi LZhuge QSha E(2018)Write Energy Reduction for PCM via Pumping Efficiency ImprovementACM Transactions on Storage10.1145/320013914:3(1-21)Online publication date: 26-Nov-2018
https://dl.acm.org/doi/10.1145/3200139
Surywanshi JPadole D(2018)Signaling Protocol Specification for Signaling Approach-Based Virtual Output Queue Router ArchitectureInformation and Communication Technology for Competitive Strategies10.1007/978-981-13-0586-3_3(21-29)Online publication date: 31-Aug-2018
https://doi.org/10.1007/978-981-13-0586-3_3
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents