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Retargetable static timing analysis for embedded software

Published: 30 September 2001 Publication History

Abstract

This paper presents a novel approach for retargetable static software timing analysis. Specifically, we target the problem of determining bounds on the execution time of a program on modern processors, and solve this problem in a retargetable software development environment. Another contribution of this paper is the modeling of important features in contemporary architectures, such as branch prediction, predication, and instruction pre-fetching, which have great impact on system performance, and have been rarely handled thus far. These ideas allow to build a timing analysis tool that is efficient, accurate, modular and retargetable. We present preliminary results for sample embedded programs to demonstrate the applicability of the proposed approach.

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cover image ACM Conferences
ISSS '01: Proceedings of the 14th international symposium on Systems synthesis
September 2001
290 pages
ISBN:1581134185
DOI:10.1145/500001
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 30 September 2001

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ISSS01: 14th International Symposium on System Synthesis
September 30 - October 3, 2001
P.Q., Montréal, Canada

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Overall Acceptance Rate 38 of 71 submissions, 54%

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Cited By

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  • (2016)Performance Evaluation Methods for Multiprocessor System-on-Chip DesignsElectronic Design Automation for IC System Design, Verification, and Testing10.1201/b19569-9(85-98)Online publication date: 14-Apr-2016
  • (2014)Architecture-parametric timing analysis2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS.2014.6926002(189-200)Online publication date: Apr-2014
  • (2013)Software-based register file vulnerability reduction for embedded processorsACM Transactions on Embedded Computing Systems10.1145/2536747.253676013:1s(1-20)Online publication date: 6-Dec-2013
  • (2012)Performance Analysis of Reconfigurations in Adaptive Real-Time Streaming ApplicationsACM Transactions on Embedded Computing Systems10.1145/2180887.218088811S:1(1-20)Online publication date: 1-Jun-2012
  • (2011)Parametric timing analysis and its application to dynamic voltage scalingACM Transactions on Embedded Computing Systems10.1145/1880050.188006110:2(1-34)Online publication date: 7-Jan-2011
  • (2011)Static Analysis of Register File VulnerabilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.209563030:4(607-616)Online publication date: 1-Apr-2011
  • (2011)ASIP Exploration and DesignScalable Multi-core Architectures10.1007/978-1-4419-6778-7_4(81-103)Online publication date: 13-Sep-2011
  • (2010)Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution TimeIEEE Transactions on Computers10.1109/TC.2010.4459:6(855-864)Online publication date: 1-Jun-2010
  • (2010)An evaluation of free/open source static analysis tools applied to embedded software2010 11th Latin American Test Workshop10.1109/LATW.2010.5550368(1-6)Online publication date: Mar-2010
  • (2010)Statistical Performance Analysis and Estimation for Parallel Multimedia ProcessingJournal of Signal Processing Systems10.1007/s11265-008-0318-z58:2(105-116)Online publication date: 1-Feb-2010
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