Article

The standard SpecC language

Authors:

Masahiro Fujita,

Hiroshi NakamuraAuthors Info & Claims

ISSS '01: Proceedings of the 14th international symposium on Systems synthesis

Pages 81 - 86

https://doi.org/10.1145/500001.500019

Published: 30 September 2001 Publication History

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Abstract

This paper introduces SpecC language, a system level description language based on C, and its consortium, SpecC Technology Open Consortium (STOC). Currently SpecC language version 1.0 is publicly available. SpecC technology covers SpecC-based design "methodology" as well as SpecC language itself. In this paper not only SpecC language but also SpecC-based design methodology are briefly discussed. The SpecC language specification working group (LSWG) under STOC is discussing on SpecC version 2.0. We also give a summary of the discussions being made by LSWG targeting version 2.0. We plan to formally release version 2.0 in the beginning of 2002. The main goal is to precisely and exactly define the formal semantics of SpecC language especially on the semantics relating to parallel and concurrent statements and event control mechanisms. These are the issues on which SpecC version 1.0 does not give clear and concise semantics. With these clarifications given by SpecC version 2.0, varieties of supporting tools for SpecC can consistently and easily be developed.

References

[1]

R. Doemer, A. Gerstlauer, and D. Gajski, "SpecC Language Reference Manual Version 1.0," http://www.specc.gr.jp/eng/tech/SpecC_LRM.pdf.

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[2]

http://www.ics.uci.edu/~specc/reference/

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[3]

http://www.specc.gr.jp/eng/wg_lang

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Dias DLima GBarros E(2016)A Cache Design Assessment Approach for Embedded Real-Time Systems Based on Execution Time Measurement2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)10.1109/SBESC.2016.033(168-173)Online publication date: Nov-2016
https://doi.org/10.1109/SBESC.2016.033
Che-Wei Chang Domer R(2015)Communication protocol analysis of transaction-level models using Satisfiability Modulo TheoriesThe 20th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2015.7059075(606-611)Online publication date: Jan-2015
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Fowers JLiu JStitt GCorporaal HStuijk S(2014)A framework for dynamic parallelization of FPGA-accelerated applicationsProceedings of the 17th International Workshop on Software and Compilers for Embedded Systems10.1145/2609248.2609256(1-10)Online publication date: 10-Jun-2014
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The standard SpecC language

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Published In

ISSS '01: Proceedings of the 14th international symposium on Systems synthesis

September 2001

290 pages

ISBN:1581134185

DOI:10.1145/500001

General Chair:
Roman Hermida
Complutense Universidad, Madrid, Spain
,
Program Chair:
El Mostapha Aboulhamid
Université de Montréal, Québec, Canada

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 30 September 2001

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ISSS01: 14th International Symposium on System Synthesis

September 30 - October 3, 2001

P.Q., Montréal, Canada

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Dias DLima GBarros E(2016)A Cache Design Assessment Approach for Embedded Real-Time Systems Based on Execution Time Measurement2016 VI Brazilian Symposium on Computing Systems Engineering (SBESC)10.1109/SBESC.2016.033(168-173)Online publication date: Nov-2016
https://doi.org/10.1109/SBESC.2016.033
Che-Wei Chang Domer R(2015)Communication protocol analysis of transaction-level models using Satisfiability Modulo TheoriesThe 20th Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2015.7059075(606-611)Online publication date: Jan-2015
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Mhadhbi ILitayem NOthman SSaoud S(2014)Impact of Hardware/Software Partitioning and MicroBlaze FPGA Configurations on the Embedded Systems PerformancesComplex System Modelling and Control Through Intelligent Soft Computations10.1007/978-3-319-12883-2_25(711-744)Online publication date: 30-Nov-2014
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Fowers JStitt GHutchings BBetz V(2013)DynafuseProceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/2435264.2435300(201-210)Online publication date: 11-Feb-2013
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Chang CDömer R(2013)Formal Deadlock Analysis of SpecC Models Using Satisfiability Modulo TheoriesEmbedded Systems: Design, Analysis and Verification10.1007/978-3-642-38853-8_11(116-127)Online publication date: 2013
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Cong JGururaj KZhang PZou Y(2012)Task-level data model for hardware synthesis based on concurrent collectionsJournal of Electrical and Computer Engineering10.1155/2012/6918642012(6-6)Online publication date: 1-Jan-2012
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Extending the SystemC synthesis subset by object-oriented features

Automated Synthesis of Streaming Transfer Level Hardware Designs

An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis

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