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A universal technique for fast and flexible instruction-set architecture simulation

Authors:

Andreas HoffmannAuthors Info & Claims

DAC '02: Proceedings of the 39th annual Design Automation Conference

Pages 22 - 27

https://doi.org/10.1145/513918.513927

Published: 13 October 2019 Publication History

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Abstract

In the last decade, instruction-set simulators have become an essential development tool for the design of new programmable architectures. Consequently, the simulator performance is a key factor for the overall design efficiency. Based on the extremely poor performance of commonly used interpretive simulators, research work on fast compiled instruction-set simulation was started ten years ago. However, due to the restrictiveness of the compiled technique, it has not been able to push through in commercial products. This paper presents a new retargetable simulation technique which combines the performance of traditional compiled simulators with the flexibility of interpretive simulation. This technique is not limited to any class of architectures or applications and can be utilized from architecture exploration up to end-user software development. The work-flow and the applicability of the so-called just-in-time cache compiled simulation (JIT-CCS) technique will be demonstrated by means of state of the art real world architectures.

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Cited By

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Chattopadhyay AWang ZMartin G(2022)Architecture Description LanguagesHandbook of Computer Architecture10.1007/978-981-15-6401-7_18-1(1-34)Online publication date: 25-Dec-2022
https://doi.org/10.1007/978-981-15-6401-7_18-1
Cornaglia AViehl ABringmann ORosenstiel WShibuya T(2019)SIMULTimeProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3287625(526-531)Online publication date: 21-Jan-2019
https://dl.acm.org/doi/10.1145/3287624.3287625
Weinstock JLeupers RAscheid G(2017)Accelerating MPSoC Simulation Using Parallel SystemC and Processor Sleep ModelsProceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/3023973.3023975(1-6)Online publication date: 23-Jan-2017
https://dl.acm.org/doi/10.1145/3023973.3023975
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A universal technique for fast and flexible instruction-set architecture simulation

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Published In

DAC '02: Proceedings of the 39th annual Design Automation Conference

June 2002

956 pages

ISBN:1581134614

DOI:10.1145/513918

General Chair:
Bryan Ackland
Agere Systems, Inc., Holmdel, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 October 2019

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DAC02

Sponsor:

SIGDA

DAC02: 39th Design Automation Conference

June 10 - 14, 2002

Louisiana, New Orleans, USA

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DAC '02 Paper Acceptance Rate 147 of 491 submissions, 30%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

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Cited By

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Chattopadhyay AWang ZMartin G(2022)Architecture Description LanguagesHandbook of Computer Architecture10.1007/978-981-15-6401-7_18-1(1-34)Online publication date: 25-Dec-2022
https://doi.org/10.1007/978-981-15-6401-7_18-1
Cornaglia AViehl ABringmann ORosenstiel WShibuya T(2019)SIMULTimeProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3287625(526-531)Online publication date: 21-Jan-2019
https://dl.acm.org/doi/10.1145/3287624.3287625
Weinstock JLeupers RAscheid G(2017)Accelerating MPSoC Simulation Using Parallel SystemC and Processor Sleep ModelsProceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/3023973.3023975(1-6)Online publication date: 23-Jan-2017
https://dl.acm.org/doi/10.1145/3023973.3023975
Joloboff VMonin JShi X(2016)SimSoC: A Fast, Proven Faithful, Full System Virtual Prototyping FrameworkModel-Implementation Fidelity in Cyber Physical System Design10.1007/978-3-319-47307-9_5(129-156)Online publication date: 10-Dec-2016
https://doi.org/10.1007/978-3-319-47307-9_5
Ottlik SStattelmann SViehl ARosenstiel WBringmann OChatha KErnst RRaghunathan AIyer R(2014)Context-sensitive timing simulation of binary embedded softwareProceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.1145/2656106.2656117(1-10)Online publication date: 12-Oct-2014
https://dl.acm.org/doi/10.1145/2656106.2656117
Chattopadhyay A(2013)Ingredients of adaptabilityVLSI Design10.1155/2013/6836152013(10-10)Online publication date: 1-Jan-2013
https://dl.acm.org/doi/10.1155/2013/683615
Wu MFu CWang PTsay R(2013)A distributed timing synchronization technique for parallel multi-core instruction-set simulationACM Transactions on Embedded Computing Systems10.1145/2435227.243525012:1s(1-24)Online publication date: 29-Mar-2013
https://dl.acm.org/doi/10.1145/2435227.2435250
Lezuo RKrall A(2013)Using the CASM language for simulator synthesis and model verificationProceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools10.1145/2432516.2432522(1-8)Online publication date: 21-Jan-2013
https://dl.acm.org/doi/10.1145/2432516.2432522
Michel LFournel NPétrot FJerraya ACarloni LChang NFummi F(2012)Fast simulation of systems embedding VLIW processorsProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2380445.2380472(143-150)Online publication date: 7-Oct-2012
https://dl.acm.org/doi/10.1145/2380445.2380472
Kyle SBöhm IFranke BLeather HTopham N(2012)Efficiently parallelizing instruction set simulation of embedded multi-core processors using region-based just-in-time dynamic binary translationACM SIGPLAN Notices10.1145/2345141.224842247:5(21-30)Online publication date: 12-Jun-2012
https://dl.acm.org/doi/10.1145/2345141.2248422
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Instruction set compiled simulation: a technique for fast and flexible instruction set simulation