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A comparison of three verification techniques: directed testing, pseudo-random testing and property checking

Authors:

Mike G. Bartley,

Darren Galpin,

Tim BlackmoreAuthors Info & Claims

DAC '02: Proceedings of the 39th annual Design Automation Conference

Pages 819 - 823

https://doi.org/10.1145/513918.514121

Published: 10 June 2002 Publication History

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Abstract

This paper describes the verification of two versions of a bridge between two on-chip buses. The verification was performed just as the Infineon Technologies Design Centre in Bristol was introducing pseudo-random testing (using Specman) and property checking (using GateProp) into their verification flows and thus provides a good opportunity to compare these two techniques with the existing strategy of directed testing using VHDL bus functional models.

References

[1]

Bergeron, J. Writing Testbenches; functional verification of HDL models (2000), Kluwer Academic Publishers

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[2]

Bormann, J. and Spalinger, C. (2001) Formale Verifikation fuer Nicht-Formalisten (Formal Verification for Non-Formalists), Informationstechnik und Technische Informatik, volume 43, issue 1/2001, Oldenbourg Verlag

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[3]

Barrett, G. and McIsaac, A. (1997) Model Checking in a MicroProcessor Design Project, CAV'97 (Proceedings of the 9th International Conference on Computer-Aided Verification, Haifa, Israel 1997, Orna Grumberg (Ed.), Springer Lecture Notes in Computer Science 1254)

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Gandhi MMohd-Mokhtar R(2014)Reusable and design independent memory controller scoreboard using memory data hazard checks2014 IEEE Student Conference on Research and Development10.1109/SCORED.2014.7072992(1-6)Online publication date: Dec-2014
https://doi.org/10.1109/SCORED.2014.7072992
Kühne UGroße DDrechsler RBenini LDe Micheli GAl-Hashimi BMueller W(2009)Property analysis and design understandingProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874920(1246-1249)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874920
Kuhne UGrosse DDrechsler R(2008)Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking FlowProceedings of the 2008 Ninth International Workshop on Microprocessor Test and Verification10.1109/MTV.2008.17(88-93)Online publication date: 8-Dec-2008
https://dl.acm.org/doi/10.1109/MTV.2008.17
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Index Terms

A comparison of three verification techniques: directed testing, pseudo-random testing and property checking
1. Hardware
  1. Hardware validation
    1. Functional verification

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Published In

DAC '02: Proceedings of the 39th annual Design Automation Conference

June 2002

956 pages

ISBN:1581134614

DOI:10.1145/513918

General Chair:
Bryan Ackland
Agere Systems, Inc., Holmdel, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 10 June 2002

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DAC02: 39th Design Automation Conference

June 10 - 14, 2002

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DAC '02 Paper Acceptance Rate 147 of 491 submissions, 30%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Gandhi MMohd-Mokhtar R(2014)Reusable and design independent memory controller scoreboard using memory data hazard checks2014 IEEE Student Conference on Research and Development10.1109/SCORED.2014.7072992(1-6)Online publication date: Dec-2014
https://doi.org/10.1109/SCORED.2014.7072992
Kühne UGroße DDrechsler RBenini LDe Micheli GAl-Hashimi BMueller W(2009)Property analysis and design understandingProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874920(1246-1249)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874920
Kuhne UGrosse DDrechsler R(2008)Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking FlowProceedings of the 2008 Ninth International Workshop on Microprocessor Test and Verification10.1109/MTV.2008.17(88-93)Online publication date: 8-Dec-2008
https://dl.acm.org/doi/10.1109/MTV.2008.17
Bhadra JAbadir MWang LRay S(2007)A Survey of Hybrid Techniques for Functional VerificationIEEE Design & Test10.1109/MDT.2007.3024:2(112-122)Online publication date: 1-Mar-2007
https://dl.acm.org/doi/10.1109/MDT.2007.30
Zabel HRettberg AKrupp A(2007)Approach for a Formal Verification of a Bit-serial Pipelined ArchitectureEmbedded System Design: Topics, Techniques and Trends10.1007/978-0-387-72258-0_5(47-56)Online publication date: 2007
https://doi.org/10.1007/978-0-387-72258-0_5
Shen HFu YTang T(2005)Priority directed test generation for functional verification using neural networksProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120822(1052-1055)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120822
Shen HChen YHuang J(2004)EmGenProceedings of the First international conference on Embedded Software and Systems10.1007/11535409_77(528-535)Online publication date: 9-Dec-2004
https://dl.acm.org/doi/10.1007/11535409_77

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Verification Techniques for System-Level Design

Industrial Strength Formal Verification Techniques for Hardware Designs

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Analyzing encryption protocols using formal verification techniques

Verification Techniques for System-Level Design

Industrial Strength Formal Verification Techniques for Hardware Designs

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