article

Energy-conscious compilation based on voltage scaling

Authors:

N. Vijaykrishnan,

U. KremerAuthors Info & Claims

ACM SIGPLAN Notices, Volume 37, Issue 7

Pages 2 - 11

https://doi.org/10.1145/566225.513832

Published: 19 June 2002 Publication History

Abstract

As energy consumption has become a majorconstraint in current system design, it is essential to look beyond the traditional low-power circuit and architectural optimizations. Further, software is becoming an increasing portion of embedded/portable systems. Consequently, optimizing the software in conjunction with the underlying low-power hardware features such as voltage scaling is vital.In this paper, we present two compiler-directed energy optimization strategies based on voltage scaling: static voltage scaling and dynamic voltage scaling. In static voltage scaling, the compiler determines a single supply voltage level for the entire input program. We primarily aim at improving the energy consumption of a given code without increasing its execution time. To accomplish this, we employ classical loop-level compiler optimizations. However, we use these optimizations to create opportunities for voltage scaling to save energy, rather than increase program performance.In dynamic voltage scaling, the compiler can select different supply voltage levels for different parts of the code. Our compilation strategy is based on integer linear programming and can accommodate energy/performance constraints. For a benchmark suite of array-based scientific codes and embedded video/image applications, our experiments show average energy savings of 31.8% when static voltage scaling is used. Our dynamic voltage scaling strategy saves 15.3% more energy than static voltage scaling when invoked under the same performance constraints.

References

[1]

A. V. Aho, R. Sethi, and J. Ullman. Compilers: Principles, Techniques, and Tools. Addison-Wesley, 1986]]

Digital Library

[2]

S. P. Amarasinghe, J. M. Anderson, M. S. Lam, and C. W. Tseng The SUIF compiler for scalable parallel machines. In Proc.the Seventh SIAM Conference on Parallel Processing for Scientific Computing, February, 1995]]

[3]

System-level power estimation and optimization. In Proc. International Symposium Low Power Electronics and Design, Monterey, CA, 1998]]

Digital Library

[4]

T. Burd and R. Brodersen. Design issues for dynamic voltage scaling. In Proceedings of 2000 International Symposium on Low Power Electronics and Design (ISLPED'00), July 2000]]

Digital Library

[5]

D. Burger, T. Austin, and S. Bennett. Evaluating future microprocessors: the SimpleScalar tool set. Technical Report CS-TR-96-103, Computer Science Dept., University of Wisconsin, Madison, July 1996]]

[6]

E. Chan, K. Govil, and H. Wasserman. Comparing algorithms for dynamic speed-setting of a low-power CPU. In Proc. the 1st ACM International Conference on Mobile Computing and Networking, pages 13--25, November 1995]]

Digital Library

[7]

R. Chen, R. Bajwa and M. J. Irwin. Architectural level power estimation and design experiments. ACM Transactions on Design Automation of Electronic Systems, 2001]]

Digital Library

[8]

A. Chandrakasan, W. J. Bowhill, and F. Fox. Design of High-Performance Microprocessor Circuits. IEEE Press, 2001]]

Digital Library

[9]

A. Chandrakasan and R. Brodersen. Low Power Digital CMOS Design. Kluwer Academic Publishers, 1995]]

Digital Library

[10]

A. P. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, and R. W. Brodersen. In Proc. Optimizing power using transformation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 1, pp. 12--30, January 1995]]

[11]

B. Childers, H. Tang, and R. Melhem. Adapting processor supply voltage to instruction-level parallelism. In Kool Chips 2000 Workshop, December 2000]]

[12]

V. Delaluz, M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, and M. J. Irwin. DRAM energy management using software and hardware directed power mode control. In Proc. the 7th International Conference on High Performance Computer Architecture, Monterrey, Mexico, January 2001]]

Digital Library

[13]

D. Duarte, N. Vijaykrishnan, M. J. Irwin and M. Kandemir. Formulation and validation of an energy dissipation model for clock generation circuitry and distribution network. In Proc. International Conference on VLSI Design, January 2001]]

Digital Library

[14]

D. Duarte, N. Vijaykrishnan and Irwin, M.J., "A Complete Phase-Locked Loop Power Consumption Model", To appear in Proc. Design, Automation and Test in Europe Conference, March 2002]]

Digital Library

[15]

S. Ghiasi, J. Casmira, and D. Grunwald. Using IPC variation in workloads with externally specified rates to reduce power consumption. In Workshop on Complexity Effective Design, June 2000]]

[16]

K. Govil, E. Chan, and H. Wasserman. Comparing algorithms for dynamic speed-setting of a low-power CPU. In the 1st ACM International Conference on Mobile Computing and Networking (MOBICOM-95), pages 13--25, November 1995]]

Digital Library

[17]

D. Grunwald, P. Levis, K. Farkas, C. Morrey III, and M. Neufeld. Policies for dynamic clock scheduling. In Proceedings of the 4th Symposium on Operating System Design and Implementation (OSDI-2000), October 2000]]

Digital Library

[18]

J. Hom and U. Kremer Energy management of virtual memory on diskless devices. In Proc. the 2nd Workshop on Compilers and Operating Systems for Low Power, attached to PACT'01, Barcelona, Spain, September 2001]]

[19]

I. Hong, D. Kirovski, G. Qu, M. Potkonjak, and M. Srivastava. Power optimization of variable voltage core-based systems. In Proceedings of the 35th ACM/IEEE Design Automation Conference(DAC'98), pages 176--181, June 1998]]

Digital Library

[20]

C-H. Hsu, U. Kremer, and M. Hsiao. Compiler-directed dynamic frequency/voltage scheduling for energy reduction in microprocessors. In Proc. International Symposium on Low Power Electronics and Design, August 2001]]

Digital Library

[21]

C-H. Hsu and U. Kremer. Dynamic Voltage and frequency scaling for scientific applications. In Proc. the Workshop on Languages and Compilers for Parallel Computing, August 2001]]

[22]

C.-H. Hsu and U. Kremer. Compiler-Directed Dynamic Voltage Scaling Based on Program Regions. Technical Report DCS-TR-461. Department of Computer Science, Rutgers University. Nov 2001]]

Digital Library

[23]

C.-H. Hsu and U. Kremer.Single Region vs. Multiple Regions: A Comparison of Different Compiler-Directed Dynamic Voltage Scheduling Approaches. Workshop on Power-Aware Computer Systems (PACS '02) Feb 2002]]

[24]

P. Stanley-Marbell, M. Hsiao and U. Kremer. A Hardware Architecture for Dynamic Performance and Energy Adaption. Workshop on Power-Aware Computer Systems (PACS '02) Feb 2002]]

[25]

T. Ishihara and H. Yasuura. Voltage scheduling problem for dynamically variable voltage processors. In International Symposium on Low Power Electronics and Design (ISLPED-98), pages 197--202, August 1998]]

Digital Library

[26]

M. Kandemir, N. Vijaykrishnan, M. J. Irwin, and W. Ye. Influence of compiler optimizations on system power. In Proc. the 37th Design Automation Conference, Los Angeles, California USA, June 5-9, 2000]]

Digital Library

[27]

W. Li. Compiling for NUMA parallel machines. Ph.D. Thesis, Cornell University, 1993]]

Digital Library

[28]

A. Manzak and C. Chakrabarti. Variable voltage task scheduling for minimizing energy or minimizing power. In Proceeding of the International Conference on Acoustics, Speech and Signal Processing, June 2000]]

Digital Library

[29]

D. Marculescu. Power efficient processors using multiple supply voltages. In Proc. the 1st Workshop on Compilers and Operating Systems for Low Power, attached to PACT'00, 2000]]

[30]

D. Marculescu. On the use of microarchitecture-driven dynamic voltage scaling. In Workshop on Complexity-Effective Design, June 2000]]

[31]

D. Mossé, H. Aydin, B. Childers, and R. Melhem. Compiler-assisted dynamic power-aware scheduling for real-time applications. In Workshop on Compiler and Operating Systems for Low Power (COLP'00), October 2000]]

[32]

T. Okuma, T. Ishihara, and H. Yasuura. Real-time task scheduling for a variable voltage processor. In Proceedings of the 12th International Symposium on System Synthesis (ISSS'99), 1999]]

Digital Library

[33]

T. Pering, T. Burd, and R. Brodersen. Dynamic voltage scaling and the design of a low-power microprocessor system. In Proc. Power Driven Microarchitecture Workshop, attached to ISCA'98, June 1998]]

[34]

J. Pouwelse, K. Langendoen, and H. Sips. Voltage scaling on a low-power microprocessor. In International Symposium on Mobile Multimedia Systems & Applications (MMSA'2000), November 2000]]

[35]

H. Schwab. lp_solve Mixed Integer Linear Program Solver, ftp://ftp.es.ele.tue.nl/pub/lp_solve/]]

[36]

W-T. Shiue and C. Chakrabarti. Memory exploration for low power, embedded systems, Technical Report CLPE-TR-9-1999-20, Arizona State University, 1999]]

Digital Library

[37]

V. Swaminathan and K. Chakrabarty. Investigating the effect of voltage switching on low-energy task scheduling in hard real-time systems. In Asia South Pacific Design Automation Conference (ASP-DAC'01), January/February 2001]]

Digital Library

[38]

V. Tiwari, S. Malik, A. Wolfe, and T. C. Lee. Instruction level power analysis and optimization of software, Journal of VLSI Signal Processing Systems, Vol. 13, No. 2, August 1996]]

[39]

N. Vijaykrishnan, M. Kandemir, M. J. Irwin, H. S. Kim, and W. Ye. Energy-driven integrated hardware-software optimizations using SimplePower. In Proc. the International Symposium on Computer Architecture, Vancouver, British Columbia, June 2000]]

Digital Library

[40]

M. Weiser, B. Welch, A. Demers, and S. Shenker. Scheduling for reduced CPU energy. In Proc. the USENIX Symposium on Operating Systems Design and Implementation, 1994, pp. 13--23]]

Digital Library

[41]

M. Wolfe. High Performance Compilers for Parallel Computing, Addison-Wesley Publishing Company, 1996]]

Digital Library

[42]

F. Yao, A. Demers, and S. Shenker. A scheduling model for reduced cpu energy. In IEEE Annual Symposium on Foundations of Computer Science, pages 374--382, October 1995]]

Digital Library

Cited By

Hajiamini SShirazi BCrandall AGhasemzadeh HCain C(2018)Impact of Cache Voltage Scaling on Energy-Time Pareto Frontier in Multicore SystemsSustainable Computing: Informatics and Systems10.1016/j.suscom.2018.02.01118(54-65)Online publication date: Jun-2018
https://doi.org/10.1016/j.suscom.2018.02.011
Wang ZZhao WWang HCheng L(2018)Three-level performance optimization for heterogeneous systems based on software prefetching under power constraintsFuture Generation Computer Systems10.1016/j.future.2018.03.00986(51-58)Online publication date: Sep-2018
https://doi.org/10.1016/j.future.2018.03.009
Bessa TQuintão PFrank MMagno Quintão Pereira F(2016)JetsonLeap: A Framework to Measure Energy-Aware Code Optimizations in Embedded and Heterogeneous SystemsProgramming Languages10.1007/978-3-319-45279-1_2(16-30)Online publication date: 17-Sep-2016
https://doi.org/10.1007/978-3-319-45279-1_2
Show More Cited By

Index Terms

Energy-conscious compilation based on voltage scaling
1. Software and its engineering
  1. Software notations and tools
    1. Compilers

Recommendations

Energy-conscious compilation based on voltage scaling
LCTES/SCOPES '02: Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems

As energy consumption has become a majorconstraint in current system design, it is essential to look beyond the traditional low-power circuit and architectural optimizations. Further, software is becoming an increasing portion of embedded/portable ...
Quasi-static voltage scaling for energy minimization with time constraints

Supply voltage scaling and adaptive body biasing (ABB) are important techniques that help to reduce the energy dissipation of embedded systems. This is achieved by dynamically adjusting the voltage and performance settings according to the application ...
Compiler-Directed Energy Reduction Using Dynamic Voltage Scaling and Voltage Islands for Embedded Systems

Addressing power and energy consumption related issues early in the system design flow ensures good design and minimizes iterations for faster turnaround time. In particular, optimizations at software level, e.g., those supported by compilers, are very ...

Comments

Information & Contributors

Information

Published In

cover image ACM SIGPLAN Notices

ACM SIGPLAN Notices Volume 37, Issue 7

July 2002

232 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/566225

Issue’s Table of Contents

LCTES/SCOPES '02: Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
June 2002
244 pages
ISBN:1581135270
DOI:10.1145/513829
Conference Chairs:
Peter Marwedel
University of Dortmund
,
Srinivas Devadas
Massachusetts Institute of Technology

Copyright © 2002 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 June 2002

Published in SIGPLAN Volume 37, Issue 7

Check for updates

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

77
Total Citations
View Citations
755
Total Downloads

Downloads (Last 12 months)11
Downloads (Last 6 weeks)2

Reflects downloads up to 13 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Hajiamini SShirazi BCrandall AGhasemzadeh HCain C(2018)Impact of Cache Voltage Scaling on Energy-Time Pareto Frontier in Multicore SystemsSustainable Computing: Informatics and Systems10.1016/j.suscom.2018.02.01118(54-65)Online publication date: Jun-2018
https://doi.org/10.1016/j.suscom.2018.02.011
Wang ZZhao WWang HCheng L(2018)Three-level performance optimization for heterogeneous systems based on software prefetching under power constraintsFuture Generation Computer Systems10.1016/j.future.2018.03.00986(51-58)Online publication date: Sep-2018
https://doi.org/10.1016/j.future.2018.03.009
Bessa TQuintão PFrank MMagno Quintão Pereira F(2016)JetsonLeap: A Framework to Measure Energy-Aware Code Optimizations in Embedded and Heterogeneous SystemsProgramming Languages10.1007/978-3-319-45279-1_2(16-30)Online publication date: 17-Sep-2016
https://doi.org/10.1007/978-3-319-45279-1_2
Alam MSalehi M(2015)Functional cores: Trade a little performance to save power2015 23rd Iranian Conference on Electrical Engineering10.1109/IranianCEE.2015.7146300(679-683)Online publication date: May-2015
https://doi.org/10.1109/IranianCEE.2015.7146300
Gastel BKersten REekelen M(2015)Using Dependent Types to Define Energy Augmented Semantics of Programs4th International Workshop on Foundational and Practical Aspects of Resource Analysis - Volume 996410.1007/978-3-319-46559-3_2(20-39)Online publication date: 11-Apr-2015
https://dl.acm.org/doi/10.1007/978-3-319-46559-3_2
Själander MMartonosi MKaxiras S(2014)Power-Efficient Computer Architectures: Recent AdvancesSynthesis Lectures on Computer Architecture10.2200/S00611ED1V01Y201411CAC0309:3(1-96)Online publication date: Dec-2014
https://doi.org/10.2200/S00611ED1V01Y201411CAC030
Srikant YAnanda Vardhan K(2009)Energy-Aware Compiler OptimizationsThe Compiler Design Handbook10.1201/9781420043839.ch7(7-1-7-36)Online publication date: 7-Dec-2009
https://doi.org/10.1201/9781420043839.ch7
Grosse PDurand YFeautrier P(2009)Methods for power optimization in SOC-based data flow systemsACM Transactions on Design Automation of Electronic Systems10.1145/1529255.152926014:3(1-20)Online publication date: May-2009
https://doi.org/10.1145/1529255.1529260
Liu KMahmoud KYoo JLiu Y(2023)Vincent: Green hot methods in the JVMScience of Computer Programming10.1016/j.scico.2023.102962230(102962)Online publication date: Aug-2023
https://doi.org/10.1016/j.scico.2023.102962
Wang ZSong XCheng LWang H(2021)Activity-Driven Task Allocation in Energy-Constrained Heterogeneous GPUs SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.304025440:11(2357-2371)Online publication date: Nov-2021
https://doi.org/10.1109/TCAD.2020.3040254
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Issue’s Table of Contents