Article

Free access

Evaluating the performance of four snooping cache coherency protocols

Authors:

R. H. KatzAuthors Info & Claims

ISCA '89: Proceedings of the 16th annual international symposium on Computer architecture

Pages 2 - 15

https://doi.org/10.1145/74925.74927

Published: 01 April 1989 Publication History

Abstract

Write-invalidate and write-broadcast coherency protocols have been criticized for being unable to achieve good bus performance across all cache configurations. In particular, write-invalidate performance can suffer as block size increases; and large cache sizes will hurt write-broadcast. Read-broadcast and competitive snooping extensions to the protocols have been proposed to solve each problem.

Our results indicate that the benefits of the extensions are limited. Read-broadcast reduces the number of invalidation misses, but at a high cost in processor lockout from the cache. The net effect can be an increase in total execution cycles. Competitive snooping benefits only those programs with high per-processor locality of reference to shared data. For programs characterized by inter-processor contention for shared addresses, competitive snooping can degrade performance by causing a slight increase in bus utilization and total execution time.

References

[1]

A. Agarwal, J. Hennessy and M. Horowitz, "Cache Performance of Operation System and Multiprogramming Workloads", ACM Transactions on Computer Systems, 6, 4 (November 1988), 393-43 1.

Digital Library

[2]

C. Alexander, W. Keshlear, F. Cooper and F. Briggs, "Cache Memory Performance in a UNIX Environment", Computer Architecture News, 14,3 (June 1986), 14-70.

Digital Library

[3]

J. Archibald and J. Baa; "An Evaluation of Cache Coherence Solutions in Shared-Bus Multiprocessors", ACM Transactions on Computer Systems, 4, 4 (November 1986), 273-298.

Digital Library

[4]

A. Casotto, F. Romeo and A. Sangiovannivincente1li, "A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells, Proceedings of the IEEE International Conference on Computer- Aided Design, Santa Clara, CA (November 1986), 30-33.

[5]

S. Devadas and A. R. Newton, "Topological Optimization of Multiple Level Array Logic", IEEE Transactions on Computer- Aided Design (November 1987).

Digital Library

[6]

S. J. Eggers and R. H. Katz, "A Characterization of Sharing in Parallel Programs and its Application to Coherency Protocol Evaluation", Proceedings of the 15th Annual International Symposium on Computer Architecture, Honolulu HA (May 1988), 373-383.

Digital Library

[7]

S. J. Eggers, "Simulation Analysis of Data Sharing in Shared Memory Multiprocessors", Ph.D. thesis, University of California, Berkeley (March 1989).

Digital Library

[8]

S. J. Eggers and R. H. Katz, "The Effect of Sharing on the Cache and Bus Performance of Parallel Programs", Proceedings of the 3rd International Conference on Architectural Support for Programming Languages and Operating Systems, Boston MA (April 1989).

Digital Library

[9]

G. A. Gibson, "SpurBus Specification", to appear as Computer Science Division Technical Report, University of California, Berkeley (December 1988).

[10]

J. R. GOOdIIlNl, "Cache Memory Optimization to Reduce Processor/Memory Traffic", Journal of VLSI and Computer Systems, 2,1 & 2 (1987), 61-86.

Digital Library

[11]

J. R. Goodman and P. J. Woest, "The Wisconsin Multicube: A New Large-Scale Cache-Coherent Multiprocessor", Proceedings 15th Annual International Symposium on Computer Architecture, Honolulu HA (May 1988), 422-43 1.

Digital Library

[12]

M. D. Hill, S. J. Eggeis, J. R. Lams, G. S. Taylor, G. Adams, B. K. Bose, G. A. Gibson, P. M. Hansen, J. Keller, S. I. Kong, C. G. Lee, D. Lee, J. M. Pendleton, S. A. Ritchie, D. A. Wood, B. G. Zom, P. N. Hilfinger, D. Hodges, R. H. Katz, J. Ousterhout and D. A. Patterson, "SPUR: A VLSI Multiprocessor Workstation", IEEE Computer, 19, 11 (November 1986), 8-22.

Digital Library

[13]

M. D. Hill, "Aspects of Cache Memory and Instruction Buffer Performance", Technical Report No. UCB/Computer Science Dpt. 87138 1, University of California, Berkeley (November 1987).

Digital Library

[14]

A. R. Karlin, M. S. Manasse, L. Rudolph and D. D. Sleator, "Competitive Snoopy Caching", Proceedings of the 27th Annual Symposium on Foundations of Computer Science, Toronto, Canada (October 1986), m-254.

Digital Library

[15]

A. R. Karlin, M. S. Manasse, L. Rudolph and D. D. Sleator, "Competitive Snoopy Caching", Algorithmica, 3 (1988), 79- 119.

Digital Library

[16]

R. Katz, S. Eggers, D. Wood, C. L. Perkins and R. Sheldon, "Implementing a Cache Consistency Protocol", Proceedings of the 12th Annual International Symposium on Computer Architecture, 13, 3 (June 1985), 276-283.

Digital Library

[17]

H. T. Ma, S. Devadas, R. Wei and A. Sangiovanni-Vincentelli, "Logic VerXcation Algorithms and their Parallel Implementation", Proceedings of the 24th Design Automation Conference (July 1987), 283-290.

Digital Library

[18]

S. McGrogan, R. Olson and N. Toda, "Parallelizing Large Existing Programs - Methodology and Experiences", Proceedings of Spring COMPCON (March 1986), 458-466.

[19]

D. A. Patterson, "Reduced Instruction Computers", Communications of the ACM, 28,1 (January 1985), 8-21.

Digital Library

[20]

Z. Segall and L. Rudolph, "Dynamic Decentralized Cache Schemes for an MIMD Parallel Processor", Proceedings of the 11th International Symposium on Computer Architecture, 12,3 (June 1984), 340-347.

Digital Library

[21]

A. J. Smith, "Line (Block) Size Choice for CPU Caches", IEEE Trans. on Computers, C-36,9 (September 1987), 1063-1075.

Digital Library

[22]

C. P. Thacker, L. C. Stewart and E. H. Satterthwaite, Jr, "Firefly: A Multiprocessor Workstation", IEEE Transactions on Computers, 37,8 (August 1988), 909920.

Digital Library

[23]

D. A. Wood, S. J. Eggers and G. A. Gibson, "SPUR Memory System Architecture", Technical Report No. UCB/Computer Science Dptf 87/394, University of California, Berkeley (December 1987).

Digital Library

Cited By

Srivatsa AMansour MRheindt SGabriel DWild THerkersdorf A(2021)DynaCo: Dynamic Coherence Management for Tiled Manycore ArchitecturesInternational Journal of Parallel Programming10.1007/s10766-020-00688-6Online publication date: 3-Jan-2021
https://doi.org/10.1007/s10766-020-00688-6
Srivatsa ARheindt SGabriel DWild THerkersdorf A(2019)CoD: Coherence-on-Demand – Runtime Adaptable Working Set Coherence for DSM-Based Manycore ArchitecturesEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-030-27562-4_2(18-33)Online publication date: 8-Aug-2019
https://doi.org/10.1007/978-3-030-27562-4_2
Ascheid GLeupers RZhang DZhang HCastrillon JKempf TVanthournout B(2011)Optimized Communication Architecture of MPSoCs with a Hardware SchedulerInternational Journal of Embedded and Real-Time Communication Systems10.4018/jertcs.20110701012:3(1-20)Online publication date: 1-Jul-2011
https://dl.acm.org/doi/10.4018/jertcs.2011070101
Show More Cited By

Index Terms

Evaluating the performance of four snooping cache coherency protocols
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Buses and high-speed links
  2. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

Recommendations

Evaluating the performance of four snooping cache coherency protocols
Special Issue: Proceedings of the 16th annual international symposium on Computer Architecture

Write-invalidate and write-broadcast coherency protocols have been criticized for being unable to achieve good bus performance across all cache configurations. In particular, write-invalidate performance can suffer as block size increases; and large ...
Evaluating the Performance of Four Snooping Cache Coherency Protocols
Techniques for Improving Performance of Hybrid Snooping Cache Protocols

Bus-based multiprocessors constitute a cost-effective class of shared-memory multiprocessors. Private caches are the key to an efficient utilization of the shared bus, and most such systems use a write-invalidate cache-coherence protocol to keep the ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ISCA '89: Proceedings of the 16th annual international symposium on Computer architecture

April 1989

426 pages

ISBN:0897913191

DOI:10.1145/74925

Chairman:
Jean-Claude Syre

ACM SIGARCH Computer Architecture News Volume 17, Issue 3
Special Issue: Proceedings of the 16th annual international symposium on Computer Architecture
June 1989
400 pages
ISSN:0163-5964
DOI:10.1145/74926
Editor:
Jean-Claude Syre
Issue’s Table of Contents

Copyright © 1989 Authors.

Sponsors

SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS: Computer Society

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1989

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Acceptance Rates

Overall Acceptance Rate 543 of 3,203 submissions, 17%

Upcoming Conference

ISCA '25

Sponsor:
sigarch

The 52nd Annual International Symposium on Computer Architecture

June 21 - 25, 2025

Tokyo , Japan

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

65
Total Citations
View Citations
1,141
Total Downloads

Downloads (Last 12 months)88
Downloads (Last 6 weeks)14

Reflects downloads up to 11 Aug 2024

Other Metrics

View Author Metrics

Citations

Cited By

Srivatsa AMansour MRheindt SGabriel DWild THerkersdorf A(2021)DynaCo: Dynamic Coherence Management for Tiled Manycore ArchitecturesInternational Journal of Parallel Programming10.1007/s10766-020-00688-6Online publication date: 3-Jan-2021
https://doi.org/10.1007/s10766-020-00688-6
Srivatsa ARheindt SGabriel DWild THerkersdorf A(2019)CoD: Coherence-on-Demand – Runtime Adaptable Working Set Coherence for DSM-Based Manycore ArchitecturesEmbedded Computer Systems: Architectures, Modeling, and Simulation10.1007/978-3-030-27562-4_2(18-33)Online publication date: 8-Aug-2019
https://doi.org/10.1007/978-3-030-27562-4_2
Ascheid GLeupers RZhang DZhang HCastrillon JKempf TVanthournout B(2011)Optimized Communication Architecture of MPSoCs with a Hardware SchedulerInternational Journal of Embedded and Real-Time Communication Systems10.4018/jertcs.20110701012:3(1-20)Online publication date: 1-Jul-2011
https://dl.acm.org/doi/10.4018/jertcs.2011070101
Bein WHatta NHernandez-Cons NIto HKasahara SKawahara J(2011)An online algorithm optimally self-tuning to congestion for power management problemsProceedings of the 9th international conference on Approximation and Online Algorithms10.1007/978-3-642-29116-6_4(35-48)Online publication date: 8-Sep-2011
https://dl.acm.org/doi/10.1007/978-3-642-29116-6_4
Paton NBuenabad-Chavez JChen MRaman VSwart GNarang IYellin DFernandes A(2009)Autonomic query parallelization using non-dedicated computersThe VLDB Journal — The International Journal on Very Large Data Bases10.1007/s00778-007-0090-x18:1(119-140)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1007/s00778-007-0090-x
Rothman JSmith A(2009)MinervaProceedings of the 4th International Symposium on High Performance Computing10.1007/3-540-47847-7_8(64-77)Online publication date: 18-May-2009
https://dl.acm.org/doi/10.1007/3-540-47847-7_8
Radulovic MTomasevic M(2007)Towards an Improved Integrated Coherence and Speculation ProtocolEUROCON 2007 - The International Conference on "Computer as a Tool"10.1109/EURCON.2007.4400373(405-412)Online publication date: Sep-2007
https://doi.org/10.1109/EURCON.2007.4400373
Pan GXie LDou QHe E(2006)A new hybrid directory scheme for shared memory multi-processorsProceedings of the First international computer science conference on Theory and Applications10.1007/11753728_50(498-504)Online publication date: 8-Jun-2006
https://dl.acm.org/doi/10.1007/11753728_50
Nurvitadhi EChalainanont NLu SArvind Rudolph L(2005)Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-CProceedings of the 19th annual international conference on Supercomputing10.1145/1088149.1088152(12-20)Online publication date: 20-Jun-2005
https://dl.acm.org/doi/10.1145/1088149.1088152
Zahran M(2003)On cache memory hierarchy for Chip-MultiprocessorACM SIGARCH Computer Architecture News10.1145/773365.77337031:1(39-48)Online publication date: 1-Mar-2003
https://dl.acm.org/doi/10.1145/773365.773370
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents