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Architectural and organizational tradeoffs in the design of the MultiTitan CPU

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N. P. JouppiAuthors Info & Claims

ISCA '89: Proceedings of the 16th annual international symposium on Computer architecture

Pages 281 - 289

https://doi.org/10.1145/74925.74957

Published: 01 April 1989 Publication History

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Abstract

This paper describes the architectural and organizational tradeoffs made during the design of the MultiTitan, and provides data supporting the decisions made. These decisions covered the entire space of processor design, from the instruction set and virtual memory architecture through the pipeline and organization of the machine. In particular, some of the tradeoffs involved the use of an on-chip instruction cache with off-chip TLB and floating-point unit, the use of direct-mapped instead of associative caches, the use of 64-bit vs. 32-bit data bus, and the implementation of hardware pipeline interlocks.

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Kaxiras SRos A(2013)A new perspective for efficient virtual-cache coherenceACM SIGARCH Computer Architecture News10.1145/2508148.248596841:3(535-546)Online publication date: 23-Jun-2013
https://dl.acm.org/doi/10.1145/2508148.2485968
Kaxiras SRos AMendelson A(2013)A new perspective for efficient virtual-cache coherenceProceedings of the 40th Annual International Symposium on Computer Architecture10.1145/2485922.2485968(535-546)Online publication date: 23-Jun-2013
https://dl.acm.org/doi/10.1145/2485922.2485968
Peir JHsu WSmith A(1999)Functional Implementation Techniques for CPU Cache MemoriesIEEE Transactions on Computers10.1109/12.75265148:2(100-110)Online publication date: 1-Feb-1999
https://dl.acm.org/doi/10.1109/12.752651
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Architectural and organizational tradeoffs in the design of the MultiTitan CPU

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Published In

ISCA '89: Proceedings of the 16th annual international symposium on Computer architecture

April 1989

426 pages

ISBN:0897913191

DOI:10.1145/74925

Chairman:
Jean-Claude Syre

ACM SIGARCH Computer Architecture News Volume 17, Issue 3
Special Issue: Proceedings of the 16th annual international symposium on Computer Architecture
June 1989
400 pages
ISSN:0163-5964
DOI:10.1145/74926
Editor:
Jean-Claude Syre
Issue’s Table of Contents

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1989

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Kaxiras SRos A(2013)A new perspective for efficient virtual-cache coherenceACM SIGARCH Computer Architecture News10.1145/2508148.248596841:3(535-546)Online publication date: 23-Jun-2013
https://dl.acm.org/doi/10.1145/2508148.2485968
Kaxiras SRos AMendelson A(2013)A new perspective for efficient virtual-cache coherenceProceedings of the 40th Annual International Symposium on Computer Architecture10.1145/2485922.2485968(535-546)Online publication date: 23-Jun-2013
https://dl.acm.org/doi/10.1145/2485922.2485968
Peir JHsu WSmith A(1999)Functional Implementation Techniques for CPU Cache MemoriesIEEE Transactions on Computers10.1109/12.75265148:2(100-110)Online publication date: 1-Feb-1999
https://dl.acm.org/doi/10.1109/12.752651
Jouppi N(1998)Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers25 years of the international symposia on Computer architecture (selected papers)10.1145/285930.285998(388-397)Online publication date: 1-Aug-1998
https://dl.acm.org/doi/10.1145/285930.285998
Juan TLang TNavarro J(1996)The difference-bit cacheACM SIGARCH Computer Architecture News10.1145/232974.23298624:2(114-120)Online publication date: 1-May-1996
https://dl.acm.org/doi/10.1145/232974.232986
Juan TLang TNavarro JBaer J(1996)The difference-bit cacheProceedings of the 23rd annual international symposium on Computer architecture10.1145/232973.232986(114-120)Online publication date: 15-May-1996
https://dl.acm.org/doi/10.1145/232973.232986
Seznec A(1995)DASC cacheProceedings of the 1st IEEE Symposium on High-Performance Computer Architecture10.5555/527072.822598Online publication date: 22-Jan-1995
https://dl.acm.org/doi/10.5555/527072.822598
Jouppi N(1993)Cache write policies and performanceACM SIGARCH Computer Architecture News10.1145/173682.16515421:2(191-201)Online publication date: 1-May-1993
https://dl.acm.org/doi/10.1145/173682.165154
Jouppi NSmith A(1993)Cache write policies and performanceProceedings of the 20th annual international symposium on computer architecture10.1145/165123.165154(191-201)Online publication date: 1-Jun-1993
https://dl.acm.org/doi/10.1145/165123.165154
Chen JBorg AJouppi N(1992)A simulation based study of TLB performanceACM SIGARCH Computer Architecture News10.1145/146628.13970820:2(114-123)Online publication date: 1-Apr-1992
https://dl.acm.org/doi/10.1145/146628.139708
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