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A dynamic storage scheme for conflict-free vector access

Authors:

D. T. Harper,

D. A. LinebargerAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 17, Issue 3

Pages 72 - 77

https://doi.org/10.1145/74926.74934

Published: 01 April 1989 Publication History

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Abstract

Previous investigations into data storage schemes have focused on finding a storage scheme that permits conflict-free access for a set of frequently encountered access patterns. This paper considers an alternative approach. Rather than forcing a single storage scheme to be used for all access patterns, conflict-free accesses of any constant stride can be made by selecting a storage scheme for each vector based on the accessing patterns used with that vector.

By factoring the stride into two components, one a power of 2 and the other relatively prime to 2, a storage scheme can be synthesized which allows conflict-free access to the vector using the specified stride. All such schemes are based on a variation of the row rotation mechanism proposed by Budnik and Kuck[1]. Each storage scheme is based on two parameters, one describes the type of rotation to perform and the other describes the amount of memory to be rotated as a single block. Hardware required to implement this storage scheme is efficient.

The performance of the memory under access strides other than the stride used to specify the storage scheme is also considered. This models a vector being accessed with multiple strides, in particular the row/column access of a matrix, and situations when the stride can not be determined prior to initializing the vector. Simulation results show that if a single buffer is added to each memory port then the average performance of the dynamic scheme surpasses that of the interleaved scheme for arbitrary stride accesses.

For dynamic storage schemes to be effective, the compiler must be able to detect information about the stride of vector accesses. In general, this is within the capabilities of current vectorizing compilers. Dynamic storage schemes also may allow more flexibility in program transformation performed by vectorizing compilers during optimization.

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Cited By

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Cabarcas FRico AEtsion YRamirez A(2010)Interleaving granularity on high bandwidth memory architecture for CMPs2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation10.1109/ICSAMOS.2010.5642060(250-257)Online publication date: Jul-2010
https://doi.org/10.1109/ICSAMOS.2010.5642060
González AAliagas CValero M(2014)A data cache with multiple caching strategies tuned to different types of localityACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2667170(217-226)Online publication date: 10-Jun-2014
https://dl.acm.org/doi/10.1145/2591635.2667170
González AValero MTopham NParcerisa JWallach SZima H(1997)Eliminating cache conflict misses through XOR-based placement functionsProceedings of the 11th international conference on Supercomputing10.1145/263580.263599(76-83)Online publication date: 11-Jul-1997
https://dl.acm.org/doi/10.1145/263580.263599
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Index Terms

A dynamic storage scheme for conflict-free vector access
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Systolic arrays
    2. Serial architectures
      1. Pipeline computing
2. Information systems
  1. Data management systems
    1. Data structures
      1. Data access methods

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ISCA '89: Proceedings of the 16th annual international symposium on Computer architecture

Previous investigations into data storage schemes have focused on finding a storage scheme that permits conflict-free access for a set of frequently encountered access patterns. This paper considers an alternative approach. Rather than forcing a single ...
Conflict-Free Vector Access Using a Dynamic Storage Scheme

An approach whereby conflict-free access of any constant stride can be made by selecting a storage scheme for each vector based on the accessing patterns used with that vector is considered. By factoring the stride into two components, one a power of 2 ...
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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 17, Issue 3

Special Issue: Proceedings of the 16th annual international symposium on Computer Architecture

June 1989

400 pages

ISSN:0163-5964

DOI:10.1145/74926

Editor:
Jean-Claude Syre

Issue’s Table of Contents

ISCA '89: Proceedings of the 16th annual international symposium on Computer architecture
April 1989
426 pages
ISBN:0897913191
DOI:10.1145/74925
Chairman:
Jean-Claude Syre

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1989

Published in SIGARCH Volume 17, Issue 3

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Cabarcas FRico AEtsion YRamirez A(2010)Interleaving granularity on high bandwidth memory architecture for CMPs2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation10.1109/ICSAMOS.2010.5642060(250-257)Online publication date: Jul-2010
https://doi.org/10.1109/ICSAMOS.2010.5642060
González AAliagas CValero M(2014)A data cache with multiple caching strategies tuned to different types of localityACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2667170(217-226)Online publication date: 10-Jun-2014
https://dl.acm.org/doi/10.1145/2591635.2667170
González AValero MTopham NParcerisa JWallach SZima H(1997)Eliminating cache conflict misses through XOR-based placement functionsProceedings of the 11th international conference on Supercomputing10.1145/263580.263599(76-83)Online publication date: 11-Jul-1997
https://dl.acm.org/doi/10.1145/263580.263599
González AAliagas CValero MValero M(1995)A data cache with multiple caching strategies tuned to different types of localityProceedings of the 9th international conference on Supercomputing10.1145/224538.224622(338-347)Online publication date: 3-Jul-1995
https://dl.acm.org/doi/10.1145/224538.224622
Lee JYoun H(1994)PSIMProceedings of the 1994 International Conference on Parallel Processing - Volume 0110.1109/ICPP.1994.171(220-223)Online publication date: 15-Aug-1994
https://dl.acm.org/doi/10.1109/ICPP.1994.171
Liu ZLi XYou JKennedy KPolychronopoulos C(1992)On storage schemes for parallel array accessProceedings of the 6th international conference on Supercomputing10.1145/143369.143421(282-291)Online publication date: 1-Aug-1992
https://dl.acm.org/doi/10.1145/143369.143421

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