Article

High throughput overlapped message passing for low density parity check codes

Authors:

Yanni Chen,

Keshab K. ParhiAuthors Info & Claims

GLSVLSI '03: Proceedings of the 13th ACM Great Lakes symposium on VLSI

Pages 245 - 248

https://doi.org/10.1145/764808.764872

Published: 28 April 2003 Publication History

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Abstract

In this paper, a systematic approach is proposed to develop high throughput decoder for structured (quasi-cyclic) low density parity check (LDPC) block codes. Based on the properties of quasi-cyclic LDPC codes, the two stages of belief propagation decoding algorithm could be overlapped and thus the overall decoding latency is reduced. To avoid the memory access conflict, the maximum concurrency of the two stages is explored by a novel scheduling algorithm. Consequently, the decoding throughput could be increased by almost twice assuming dual-port memory is available.

References

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R. G. Gallager, "Low density parity check codes," IRE Trans. Info. Theory, vol. IT-8, pp. 21--28, 1962.

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[2]

T. Zhang, and K.K. Parhi, "VLSI implementation oriented (3,k)-regular low-density parity-check codes," Proc. of 2001 IEEE Workshop on Signal Processing Systems, pp. 25--36, Sept. 2001.

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[3]

D. J. C. MacKay, R. M. Neal, "Near Shannon limit performance of low density parity check codes," Electronics Letters, vol. 32, pp. 1645, 1996.

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[4]

D. Sridhara, T. Fuja, R. M. Tanner, "Low density parity check codes from permutation matrices," 2001 Conf. on Info. Sciences and Systems, The John Hopkins University, March 2001.

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D. Hocevar, "LDPC code construction with flexible hardware implementation," to appear in Proc. of ICC'03, 2003.

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Cited By

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Hasani ALopacinski LBuchner SNolte JKraemer R(2019)A Modified Shuffling Method to Split the Critical Path Delay in Layered Decoding of QC-LDPC Codes2019 IEEE 30th Annual International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)10.1109/PIMRC.2019.8904435(1-6)Online publication date: Oct-2019
https://doi.org/10.1109/PIMRC.2019.8904435
Chen YParhi K(2004)Overlapped Message Passing for Quasi-Cyclic Low-Density Parity Check CodesIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2004.82619451:6(1106-1113)Online publication date: Jul-2004
https://doi.org/10.1109/TCSI.2004.826194
Sang-Min Kim Parhi K(2004)Overlapped Decoding for a Class of Quasi-Cyclic LDPC CodesIEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.10.1109/SIPS.2004.1363034(113-117)Online publication date: 2004
https://doi.org/10.1109/SIPS.2004.1363034
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Index Terms

High throughput overlapped message passing for low density parity check codes
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
      1. Hardware-software codesign
  2. Integrated circuits
    1. Semiconductor memory

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Published In

GLSVLSI '03: Proceedings of the 13th ACM Great Lakes symposium on VLSI

April 2003

320 pages

ISBN:1581136773

DOI:10.1145/764808

General Chair:
Mircea Stan
University of Virginia
,
Program Chairs:
David Garrett
Bell Labs Research, Lucent Technologies
,
Kazuo Nakajima
University of Maryland

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 28 April 2003

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April 28 - 29, 2003

D. C., Washington, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Hasani ALopacinski LBuchner SNolte JKraemer R(2019)A Modified Shuffling Method to Split the Critical Path Delay in Layered Decoding of QC-LDPC Codes2019 IEEE 30th Annual International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC)10.1109/PIMRC.2019.8904435(1-6)Online publication date: Oct-2019
https://doi.org/10.1109/PIMRC.2019.8904435
Chen YParhi K(2004)Overlapped Message Passing for Quasi-Cyclic Low-Density Parity Check CodesIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2004.82619451:6(1106-1113)Online publication date: Jul-2004
https://doi.org/10.1109/TCSI.2004.826194
Sang-Min Kim Parhi K(2004)Overlapped Decoding for a Class of Quasi-Cyclic LDPC CodesIEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.10.1109/SIPS.2004.1363034(113-117)Online publication date: 2004
https://doi.org/10.1109/SIPS.2004.1363034
Zhongfeng Wang Yanni Chen Parhi K(2004)Area efficient decoding of quasi-cyclic low density parity check codes2004 IEEE International Conference on Acoustics, Speech, and Signal Processing10.1109/ICASSP.2004.1327044(V-49-52)Online publication date: 2004
https://doi.org/10.1109/ICASSP.2004.1327044
Yuping Zhang Zhongfeng Wang Parhi K(2004)Efficient high-speed quasi-cyclic LDPC decoder architectureConference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004.10.1109/ACSSC.2004.1399191(540-544)Online publication date: 2004
https://doi.org/10.1109/ACSSC.2004.1399191

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The capacity of low-density parity-check codes under message-passing decoding

Reduced complexity decoding algorithms for low-density parity check codes and turbo codes

Rate-compatible punctured low-density parity-check codes with short block lengths

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