Article

Coverage directed test generation for functional verification using bayesian networks

Authors:

Avi ZivAuthors Info & Claims

DAC '03: Proceedings of the 40th annual Design Automation Conference

Pages 286 - 291

https://doi.org/10.1145/775832.775907

Published: 02 June 2003 Publication History

Abstract

Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or dynamic verification), by providing a new approach for Coverage Directed Test Generation (CDG). This approach is based on Bayesian networks and computer learning techniques. It provides an efficient way for closing a feedback loop from the coverage domain back to a generator that produces new stimuli to the tested design. In this paper, we show how to apply Bayesian networks to the CDG problem. Applying Bayesian networks to the CDG framework has been tested in several experiments, exhibiting encouraging results and indicating that the suggested approach can be used to achieve CDG goals.

References

[1]

J. Bergeron. Writing Testbenches: Functional Verification of HDL Models. Kluwer Academic Publishers, January 2000.

Digital Library

[2]

M. Bose, J. Shin, E. M. Rudnick, T. Dukes, and M. Abadir. A genetic approach to automatic bias generation for biased random instruction generation. In Proceedings of the 2001 Congress on Evolutionary Computation CEC2001, pages 442--448, May 2001.

[3]

R. G. Cowell, A. P. Dawid, S. L. Lauritzen, and D. J. Spiegelhalter. Probabilistic Networks and Expert Systems. Springer-Verlag, 1999.

Digital Library

[4]

G. Elidan, N. Lotner, N. Friedman, and D. Koller. Discovering hidden variables: A structure based approach. In Proceedings of the 13th Annual Conference on Neural Information Processing Systems, pages 479--485, 2000.

[5]

L. Fournier, Y. Arbetman, and M. Levinger. Functional verification methodology for microprocessors using the Genesys test-program generator. In Proceedings of the 1999 Design, Automation and Test in Europe Conference (DATE), pages 434--441, March 1999.

Digital Library

[6]

Z. Ghahramani. Learning dynamic Bayesian networks. In Adaptive Processing of Sequences and Data Structures, Lecture Notes in Artificial Intelligence, pages 168--197. Springer-Verlag, 1998.

Digital Library

[7]

R. Grinwald, E. Harel, M. Orgad, S. Ur, and A. Ziv. User defined coverage - a tool supported methodology for design verification. In Proceedings of the 35th Design Automation Conference, pages 158--165, June 1998.

Digital Library

[8]

A. Hartman, S. Ur, and A. Ziv. Short vs long size does make a difference. In Proceedings of the High-Level Design Validation and Test Workshop, pages 23--28, November 1999.

[9]

D. Heckerman. A tutorial on learning with Bayesian networks. Technical report, Microsoft Research, 1996.

[10]

D. Heckerman, A. Mamdani, and M. Wellman. Real-world applications of Bayesian networks. Communications of the ACM, 38(3):24--30, 1995.

Digital Library

[11]

G. Nativ, S. Mittermaier, S. Ur, and A. Ziv. Cost evaluation of coverage directed test generation for the IBM mainframe. In Proceedings of the 2001 International Test Conference, pages 793--802, October 2001.

Digital Library

[12]

J. Pearl. Probabilistic Reasoning in Intelligent Systems: Network of Plausible Inference. Morgan Kaufmann, 1988.

Digital Library

[13]

S. Tasiran, F. Fallah, D. G. Chinnery, S. J. Weber, and K. Keutzer. A functional validation technique: biased-random simulation guided by observability-based coverage. In Proceedings of the International Conference on Computer Design, pages 82--88, September 2001.

Digital Library

[14]

S. Ur and Y. Yadin. Micro-architecture coverage directed generation of test programs. In Proceedings of the 36th Design Automation Conference, pages 175--180, June 1999.

Digital Library

[15]

S. Wright. Correlation and causation. Journal of Agricultural Research, 1921.

Cited By

Xiao CDeng YYang ZChen RWang HZhao JDai HWang LTang YXu W(2024)LLM-based Processor Verification: A Case Study for Neuromorphic Processor2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546707(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546707
Wu NLi YYang HChen HDai SHao CYu CXie Y(2024)Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and ProspectACM Transactions on Design Automation of Electronic Systems10.1145/366130829:4(1-42)Online publication date: 24-Apr-2024
https://dl.acm.org/doi/10.1145/3661308
Jin SLi YChen LShi G(2024)SSFuzz:Generating syntactic and semantic seeds for RISC-V processorsProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658712(421-426)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658712
Show More Cited By

Index Terms

Coverage directed test generation for functional verification using bayesian networks
1. Hardware
  1. Hardware validation
    1. Functional verification

Recommendations

Accelerating Coverage Directed Test Generation for Functional Verification: A Neural Network-based Framework
GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSI

With increasing design complexity, the correlation between test transactions and functional properties becomes non-intuitive, hence impacting the reliability of test generation. This paper presents a modified coverage directed test generation based on an ...
Probabilistic regression suites for functional verification
DAC '04: Proceedings of the 41st annual Design Automation Conference

Random test generators are often used to create regression suites on-the-fly. Regression suites are commonly generated by choosing several specifications and generating a number of tests from each one, without reasoning which specification should be ...
The Risks of Coverage-Directed Test Case Generation
A number of structural coverage criteria have been proposed to measure the adequacy of testing efforts. In the avionics and other critical systems domains, test suites satisfying structural coverage criteria are mandated by standards. With the advent of ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '03: Proceedings of the 40th annual Design Automation Conference

June 2003

1014 pages

ISBN:1581136889

DOI:10.1145/775832

General Chair:
Ian Getreu
Ambric Inc., Portland, OR
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Luciano Lavagno
Cadence Berkeley Labs., Berkeley, CA

Copyright © 2003 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 June 2003

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

DAC03

Sponsor:

SIGDA

DAC03: 2003 40th Annual Design Automation Conference

June 2 - 6, 2003

CA, Anaheim, USA

Acceptance Rates

DAC '03 Paper Acceptance Rate 152 of 628 submissions, 24%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

143
Total Citations
View Citations
1,162
Total Downloads

Downloads (Last 12 months)49
Downloads (Last 6 weeks)5

Reflects downloads up to 09 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Xiao CDeng YYang ZChen RWang HZhao JDai HWang LTang YXu W(2024)LLM-based Processor Verification: A Case Study for Neuromorphic Processor2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546707(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546707
Wu NLi YYang HChen HDai SHao CYu CXie Y(2024)Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and ProspectACM Transactions on Design Automation of Electronic Systems10.1145/366130829:4(1-42)Online publication date: 24-Apr-2024
https://dl.acm.org/doi/10.1145/3661308
Jin SLi YChen LShi G(2024)SSFuzz:Generating syntactic and semantic seeds for RISC-V processorsProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658712(421-426)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658712
Ma RYang YLiu ZZhang JLi MHuang JLuo G(2024)VerilogReader: LLM-Aided Hardware Test Generation2024 IEEE LLM Aided Design Workshop (LAD)10.1109/LAD62341.2024.10691801(1-5)Online publication date: 28-Jun-2024
https://doi.org/10.1109/LAD62341.2024.10691801
Das SPatel HKarfa CBellamkonda KReddy RPuri DJain ASur APrajapati P(2024)RTL Simulation Acceleration with Machine Learning Models2024 25th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED60706.2024.10528688(1-7)Online publication date: 3-Apr-2024
https://doi.org/10.1109/ISQED60706.2024.10528688
Yadav DBhagat PBeniwal PSaurabh S(2024)Codriver: A Tool for Coverage-Driven Functional Verification of RISC-V ProcessorsVLSI for Embedded Intelligence10.1007/978-981-97-3756-7_13(157-169)Online publication date: 28-Oct-2024
https://doi.org/10.1007/978-981-97-3756-7_13
Xu JLiu YHe SLin HZhou YWang CCalandrino JTroncoso C(2023)MorFuzzProceedings of the 32nd USENIX Conference on Security Symposium10.5555/3620237.3620311(1307-1324)Online publication date: 9-Aug-2023
https://dl.acm.org/doi/10.5555/3620237.3620311
Hamaguchi K(2023)Parallelizing Random and SAT-based Verification Processes for Improving Toggle CoverageIPSJ Transactions on System and LSI Design Methodology10.2197/ipsjtsldm.16.4516(45-53)Online publication date: 2023
https://doi.org/10.2197/ipsjtsldm.16.45
Xie ZPan JChang CHu JChen Y(2023)The Dark Side: Security and Reliability Concerns in Machine Learning for EDAIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319917242:4(1171-1184)Online publication date: Apr-2023
https://doi.org/10.1109/TCAD.2022.3199172
Graf MAndrade Gdos Santos L(2023)EveCheck: An Event-Driven, Scalable Algorithm for Coherent Shared Memory VerificationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.317805142:2(683-696)Online publication date: Feb-2023
https://doi.org/10.1109/TCAD.2022.3178051
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents