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A basic architecture supporting LGDG computation

Authors:

Kechang Dai and

Wolfgang K. GiloiAuthors Info & Claims

ICS '90: Proceedings of the 4th international conference on Supercomputing

June 1990

Pages 23 - 33

https://doi.org/10.1145/77726.255135

Published: 01 June 1990 Publication History

Abstract

In order to combine the benefits of dataflow and control-flow computation while avoiding the pitfalls of both, the authors propose a two-level model of large-grain dataflow computation, called LGDG computation. A formalism has been provided in a previous paper to prove the determinism of parallel program execution under this model. The current paper presents the basic LGDG computer architecture which is organized at two levels, called the graph level and the node level. The kernel of the node-level architecture is characterized by its non-branch RISC (N-RISC) feature, which ensures an optimal utilization of pipeline processing. This kernel is supported by various co-processors based on the principle of function migration. We will show in this paper how the graph-level architecture can be reduced to a matching unit, extended by a writable control store, through node migration and node aggregation. As a result, the matching overhead is drastically reduced, thus eliminating the most severe bottleneck of existing 'fine-grain' dataflow computers.

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Cited By

Dai K(2005)Code parallelization for the LGDG large-grain dataflow computationCONPAR 90 — VAPP IV10.1007/3-540-53065-7_104(243-252)Online publication date: 2-Jun-2005
https://doi.org/10.1007/3-540-53065-7_104
Heath JRamamoorthy SStroud CHurt A(1997)Modeling, design, and performance analysis of a parallel hybrid data/command driven architecture system and its scalable dynamic load balancing circuitIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing10.1109/82.55936644:1(22-40)Online publication date: Jan-1997
https://doi.org/10.1109/82.559366
Zehendner EUngerer T(1992)A large-grain data flow architecture utilizing multiple levels of parallelismCompEuro 1992 Proceedings Computer Systems and Software Engineering10.1109/CMPEUR.1992.218492(23-28)Online publication date: 1992
https://doi.org/10.1109/CMPEUR.1992.218492
Show More Cited By

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A basic architecture supporting LGDG computation

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Published In

cover image ACM Conferences

ICS '90: Proceedings of the 4th international conference on Supercomputing

June 1990

492 pages

ISBN:0897913698

DOI:10.1145/77726

Chairmen:
Ahmed Sameh
Univ. of Illinois
,
Henk van der Vorst
Delft Univ. of Technology and CWI, The Netherlands

ACM SIGARCH Computer Architecture News Volume 18, Issue 3b
Special Issue: Proceedings of the 4th international conference on Supercomputing
Sept. 1990
489 pages
ISSN:0163-5964
DOI:10.1145/255129
Chairmen:
Ahmed Sameh
Univ. of Illinois at Urbana-Champaign, Urbana
,
Henk van der Vorst
Delft Univ. of Technology and CWI, The Netherlands
Issue’s Table of Contents

Copyright © 1990 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

Publication History

Published: 01 June 1990

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IC'90: ACM SIGARCH International Conference on Supercomputing

June 11 - 15, 1990

Amsterdam, The Netherlands

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Overall Acceptance Rate 629 of 2,180 submissions, 29%

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Cited By

Dai K(2005)Code parallelization for the LGDG large-grain dataflow computationCONPAR 90 — VAPP IV10.1007/3-540-53065-7_104(243-252)Online publication date: 2-Jun-2005
https://doi.org/10.1007/3-540-53065-7_104
Heath JRamamoorthy SStroud CHurt A(1997)Modeling, design, and performance analysis of a parallel hybrid data/command driven architecture system and its scalable dynamic load balancing circuitIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing10.1109/82.55936644:1(22-40)Online publication date: Jan-1997
https://doi.org/10.1109/82.559366
Zehendner EUngerer T(1992)A large-grain data flow architecture utilizing multiple levels of parallelismCompEuro 1992 Proceedings Computer Systems and Software Engineering10.1109/CMPEUR.1992.218492(23-28)Online publication date: 1992
https://doi.org/10.1109/CMPEUR.1992.218492
Ungerer TZehendner E(1991)A multi-level parallelism architectureACM SIGARCH Computer Architecture News10.1145/122576.12258519:4(86-93)Online publication date: 1-Jul-1991
https://dl.acm.org/doi/10.1145/122576.122585
Kechang Dai Giloi (1991)Confining imperative languages for parallel processingProceedings of the Fifth International Parallel Processing Symposium10.1109/IPPS.1991.153839(576-581)Online publication date: 30-Apr-1991
https://dl.acm.org/doi/10.1109/IPPS.1991.153839

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