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Compiler-directed data prefetching in multiprocessors with memory hierarchies

Authors:

Edward H. Gornish,

Elana D. Granston,

Alexander V. VeidenbaumAuthors Info & Claims

ICS '90: Proceedings of the 4th international conference on Supercomputing

Pages 354 - 368

https://doi.org/10.1145/77726.255176

Published: 01 June 1990 Publication History

Abstract

Memory hierarchies are used by multiprocessor systems to reduce large memory access times. It is necessary to automatically manage such a hierarchy, to obtain effective memory utilization. In this paper, we discuss the various issues involved in obtaining an optimal memory management strategy for a memory hierarchy. We present an algorithm for finding the earliest point in a program that a block of data can be prefetched. This determination is based on the control and data dependencies in the program. Such a method is an integral part of more general memory management algorithms. We demonstrate our method's potential by using static analysis to estimate the performance improvement afforded by our prefetching strategy and to analyze the reference patterns in a set of Fortran benchmarks. We also study the effectiveness of prefetching in a realistic shared-memory system using an RTL-level simulator and real codes. This differs from previous studies by considering prefetching benefits in the presence of network contention.

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https://dl.acm.org/doi/10.1145/3620665.3640396
Wang XTumeo ALeidel JLi JChen Y(2019)MACProceedings of the 48th International Conference on Parallel Processing10.1145/3337821.3337867(1-10)Online publication date: 5-Aug-2019
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Published In

cover image ACM Conferences

ICS '90: Proceedings of the 4th international conference on Supercomputing

June 1990

492 pages

ISBN:0897913698

DOI:10.1145/77726

Chairmen:
Ahmed Sameh
Univ. of Illinois
,
Henk van der Vorst
Delft Univ. of Technology and CWI, The Netherlands

ACM SIGARCH Computer Architecture News Volume 18, Issue 3b
Special Issue: Proceedings of the 4th international conference on Supercomputing
Sept. 1990
489 pages
ISSN:0163-5964
DOI:10.1145/255129
Chairmen:
Ahmed Sameh
Univ. of Illinois at Urbana-Champaign, Urbana
,
Henk van der Vorst
Delft Univ. of Technology and CWI, The Netherlands
Issue’s Table of Contents

Copyright © 1990 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

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Published: 01 June 1990

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IC'90

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SIGARCH

IC'90: ACM SIGARCH International Conference on Supercomputing

June 11 - 15, 1990

Amsterdam, The Netherlands

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Overall Acceptance Rate 629 of 2,180 submissions, 29%

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Cited By

Zhang YSobotka NPark SJamilan SKhan TKasikci BPokam GLitz HDevietti JTsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)RPG2: Robust Profile-Guided Runtime Prefetch GenerationProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 210.1145/3620665.3640396(999-1013)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3620665.3640396
Wang XTumeo ALeidel JLi JChen Y(2019)MACProceedings of the 48th International Conference on Parallel Processing10.1145/3337821.3337867(1-10)Online publication date: 5-Aug-2019
https://dl.acm.org/doi/10.1145/3337821.3337867
Zhou BHuang YXu JGuo SQi H(2019)Memory latency optimizations for the elementary functions on the Sunway architectureThe Journal of Supercomputing10.1007/s11227-018-02741-175:7(3917-3944)Online publication date: 1-Jul-2019
https://dl.acm.org/doi/10.1007/s11227-018-02741-1
Crago NStephenson MKeckler S(2018)Exposing Memory Access Patterns to Improve Instruction and Memory Efficiency in GPUsACM Transactions on Architecture and Code Optimization10.1145/328085115:4(1-23)Online publication date: 29-Oct-2018
https://dl.acm.org/doi/10.1145/3280851
Garcia VRico AVillavieja CCarpenter PNavarro NRamirez A(2017)Adaptive Runtime-Assisted Block Prefetching on Chip-MultiprocessorsInternational Journal of Parallel Programming10.1007/s10766-016-0431-845:3(530-550)Online publication date: 1-Jun-2017
https://dl.acm.org/doi/10.1007/s10766-016-0431-8
Touma RQueralt ACortes TPérez M(2017)Predicting Access to Persistent Objects Through Static Code AnalysisNew Trends in Databases and Information Systems10.1007/978-3-319-67162-8_7(54-62)Online publication date: 9-Sep-2017
https://doi.org/10.1007/978-3-319-67162-8_7
Zheng TNellans DZulfiqar AStephenson MKeckler S(2016)Towards high performance paged memory for GPUs2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446077(345-357)Online publication date: Mar-2016
https://doi.org/10.1109/HPCA.2016.7446077
Gu JGuo H(2013)Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor SystemsMobile and Handheld Computing Solutions for Organizations and End-Users10.4018/978-1-4666-2785-7.ch018(323-340)Online publication date: 2013
https://doi.org/10.4018/978-1-4666-2785-7.ch018
Gu JGuo H(2011)Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor SystemsInternational Journal of Handheld Computing Research10.4018/jhcr.20111001032:4(42-58)Online publication date: 1-Oct-2011
https://dl.acm.org/doi/10.4018/jhcr.2011100103
Gu JGuo H(2010)An Energy Efficient Instruction Prefetching Scheme for Embedded ProcessorsUbiquitous Computing and Multimedia Applications10.1007/978-3-642-13467-8_8(73-88)Online publication date: 2010
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