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Compile-time dynamic voltage scaling settings: opportunities and limits

Published: 09 May 2003 Publication History

Abstract

With power-related concerns becoming dominant aspects of hardware and software design, significant research effort has been devoted towards system power minimization. Among run-time power-management techniques, dynamic voltage scaling (DVS) has emerged as an important approach, with the ability to provide significant power savings. DVS exploits the ability to control the power consumption by varying a processor's supply voltage (V) and clock frequency (f). DVS controls energy by scheduling different parts of the computation to different (V, f) pairs; the goal is to minimize energy while meeting performance needs. Although processors like the Intel XScale and Transmeta Crusoe allow software DVS control, such control has thus far largely been used at the process/task level under operating system control. This is mainly because the energy and time overhead for switching DVS modes is considered too large and difficult to manage within a single program.In this paper we explore the opportunities and limits of compile-time DVS scheduling. We derive an analytical model for the maximum energy savings that can be obtained using DVS given a few known program and processor parameters. We use this model to determine scenarios where energy consumption benefits from compile-time DVS and those where there is no benefit. The model helps us extrapolate the benefits of compile-time DVS into the future as processor parameters change. We then examine how much of these predicted benefits can actually be achieved through optimal settings of DVS modes. This is done by extending the existing Mixed-integer Linear Program (MILP) formulation for this problem by accurately accounting for DVS energy switching overhead, by providing finer-grained control on settings and by considering multiple data categories in the optimization. Overall, this research provides a comprehensive view of compile-time DVS management, providing both practical techniques for its immediate deployment as well theoretical bounds for use into the future.

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  • (2023)Predict; Don't React for Enabling Efficient Fine-Grain DVFS in GPUsProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 410.1145/3623278.3624756(253-267)Online publication date: 25-Mar-2023
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  • (2018)Impact of Cache Voltage Scaling on Energy-Time Pareto Frontier in Multicore SystemsSustainable Computing: Informatics and Systems10.1016/j.suscom.2018.02.01118(54-65)Online publication date: Jun-2018
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Published In

cover image ACM SIGPLAN Notices
ACM SIGPLAN Notices  Volume 38, Issue 5
May 2003
349 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/780822
Issue’s Table of Contents
  • cover image ACM Conferences
    PLDI '03: Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
    June 2003
    360 pages
    ISBN:1581136625
    DOI:10.1145/781131
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 09 May 2003
Published in SIGPLAN Volume 38, Issue 5

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Author Tags

  1. analytical model
  2. compiler
  3. dynamic voltage scaling
  4. low power
  5. mixed-integer linear programming

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Cited By

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  • (2023)Predict; Don't React for Enabling Efficient Fine-Grain DVFS in GPUsProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 410.1145/3623278.3624756(253-267)Online publication date: 25-Mar-2023
  • (2023)Resource Optimization of Stream Processing in Layered Internet of Things2023 42nd International Symposium on Reliable Distributed Systems (SRDS)10.1109/SRDS60354.2023.00030(221-231)Online publication date: 25-Sep-2023
  • (2018)Impact of Cache Voltage Scaling on Energy-Time Pareto Frontier in Multicore SystemsSustainable Computing: Informatics and Systems10.1016/j.suscom.2018.02.01118(54-65)Online publication date: Jun-2018
  • (2018)Three-level performance optimization for heterogeneous systems based on software prefetching under power constraintsFuture Generation Computer Systems10.1016/j.future.2018.03.00986:C(51-58)Online publication date: 1-Sep-2018
  • (2015)An Overview of Architecture-Level Power- and Energy-Efficient Design Techniques10.1016/bs.adcom.2015.04.001(1-57)Online publication date: 2015
  • (2012)Temperature- and Energy-Constrained SchedulingDynamic Reconfiguration in Real-Time Systems10.1007/978-1-4614-0278-7_7(165-192)Online publication date: 30-Mar-2012
  • (2011)PI and PID Regulation Approaches for Performance-Constrained Adaptive Multiprocessor System-on-ChipIEEE Embedded Systems Letters10.1109/LES.2011.21663733:3(77-80)Online publication date: 1-Sep-2011
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  • (2008)Fine-grained energy profiling for power-aware application designACM SIGMETRICS Performance Evaluation Review10.1145/1453175.145318036:2(26-31)Online publication date: 31-Aug-2008
  • (2022)Power-Efficient Computer ArchitecturesundefinedOnline publication date: 25-Mar-2022
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