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View all- Flake PMoorby PGolson SSalz ADavidmann S(2020)Verilog HDL and its ancestors and descendantsProceedings of the ACM on Programming Languages10.1145/33863374:HOPL(1-90)Online publication date: 12-Jun-2020
- A. Edwards S(2018)Design and Verification LanguagesEDA for IC System Design, Verification, and Testing10.1201/9781420007947-15(15-1-15-28)Online publication date: 3-Oct-2018
- Parker A(1984)Automated Synthesis of Digital systemsIEEE Design & Test10.1109/MDT.1984.50056931:4(75-81)Online publication date: 1-Nov-1984
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