Article

Low cost instruction cache designs for tag comparison elimination

Authors:

Youtao Zhang and

Jun YangAuthors Info & Claims

ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

August 2003

Pages 266 - 269

https://doi.org/10.1145/871506.871572

Published: 25 August 2003 Publication History

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Abstract

Tag comparison elimination (TCE) is an effective approach to reduce I-cache energy. Current research focuses on finding good tradeoffs between hardware cost and percentage of comparisons that can be removed. For this purpose, two low cost innovations are proposed in this paper. We design a small dedicated TCE table whose size is flexible both horizontally (entry size) and vertically (number of entries). The design also minimizes interactions with the I-cache. For a 64-way 16K cache, the new design reduces the tag comparisons to 4.0% with a fraction only 20% of the hardware cost of the way memoization technique [5]. The result is 40% better compared to a recent proposed low cost design [2] of comparable hardware cost.

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Cited By

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Kim JLee JKim S(2017)TLB Index-Based Tagging for Reducing Data Cache and TLB Energy ConsumptionIEEE Transactions on Computers10.1109/TC.2016.264759266:7(1200-1211)Online publication date: 1-Jul-2017
https://doi.org/10.1109/TC.2016.2647592
Lee JKim SShanbhag NPoncino MChou PAmerasekera A(2012)Adopting TLB index-based tagging to data caches for tag energy reductionProceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design10.1145/2333660.2333716(231-236)Online publication date: 30-Jul-2012
https://dl.acm.org/doi/10.1145/2333660.2333716
Lee JHong SKim SChang NNakamura HInoue KOsada KPoncino M(2011)TLB index-based tagging for cache energy reductionProceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design10.5555/2016802.2016828(85-90)Online publication date: 1-Aug-2011
https://dl.acm.org/doi/10.5555/2016802.2016828
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Index Terms

Low cost instruction cache designs for tag comparison elimination
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Published In

ISLPED '03: Proceedings of the 2003 international symposium on Low power electronics and design

August 2003

502 pages

ISBN:158113682X

DOI:10.1145/871506

General Chairs:
Ingrid Verbauwhede
University of California, Los Angeles, CA
,
Hyung Roh
Samsung Electronics

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 25 August 2003

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ISLPED03: International Symposium on Low Power Electronics and Design

August 25 - 27, 2003

Seoul, Korea

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ISLPED '03 Paper Acceptance Rate 90 of 221 submissions, 41%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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ISLPED '24

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ACM/IEEE International Symposium on Low Power Electronics and Design

August 5 - 7, 2024

Newport Beach , CA , USA

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Cited By

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Kim JLee JKim S(2017)TLB Index-Based Tagging for Reducing Data Cache and TLB Energy ConsumptionIEEE Transactions on Computers10.1109/TC.2016.264759266:7(1200-1211)Online publication date: 1-Jul-2017
https://doi.org/10.1109/TC.2016.2647592
Lee JKim SShanbhag NPoncino MChou PAmerasekera A(2012)Adopting TLB index-based tagging to data caches for tag energy reductionProceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design10.1145/2333660.2333716(231-236)Online publication date: 30-Jul-2012
https://dl.acm.org/doi/10.1145/2333660.2333716
Lee JHong SKim SChang NNakamura HInoue KOsada KPoncino M(2011)TLB index-based tagging for cache energy reductionProceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design10.5555/2016802.2016828(85-90)Online publication date: 1-Aug-2011
https://dl.acm.org/doi/10.5555/2016802.2016828
Kim SLee JBahar RLombardi FAtienza DBrunvand E(2010)Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded systemProceedings of the 20th symposium on Great lakes symposium on VLSI10.1145/1785481.1785542(257-262)Online publication date: 16-May-2010
https://dl.acm.org/doi/10.1145/1785481.1785542
Wang MWang YLiu DQin ZShao Z(2010)Compiler-assisted leakage-aware loop scheduling for embedded VLIW DSP processorsJournal of Systems and Software10.1016/j.jss.2009.11.72783:5(772-785)Online publication date: 1-May-2010
https://dl.acm.org/doi/10.1016/j.jss.2009.11.727
Zhang MChang XZhang GMarculescu DRaghunathan AKeshavarzi ANarayanan V(2007)Reducing cache energy consumption by tag encoding in embedded processorsProceedings of the 2007 international symposium on Low power electronics and design10.1145/1283780.1283860(367-370)Online publication date: 27-Aug-2007
https://dl.acm.org/doi/10.1145/1283780.1283860
Wang MShao ZXue CSha E(2007)Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP ProcessorsProceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications10.1109/RTCSA.2007.60(12-19)Online publication date: 21-Aug-2007
https://dl.acm.org/doi/10.1109/RTCSA.2007.60
Akaaboune ABotros NAlghazo J(2004)Tag skipping technique using WTS buffer for optimal low power cache designRecords of the 2004 International Workshop on Memory Technology, Design and Testing, 2004.10.1109/MTDT.2004.1327978(13-18)Online publication date: 2004
https://doi.org/10.1109/MTDT.2004.1327978

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Reducing I-cache energy of multimedia applications through low cost tag comparison elimination

A Multistep Tag Comparison Method for a Low-Power L2 Cache

Cost-sensitive cache replacement algorithms

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Reducing I-cache energy of multimedia applications through low cost tag comparison elimination

A Multistep Tag Comparison Method for a Low-Power L2 Cache

Cost-sensitive cache replacement algorithms

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