article

A trace-level value predictor for Contrail processors

Authors:

Takenori Koushiro,

Toshinori Sato,

Itsujiro AritaAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 31, Issue 3

Pages 42 - 47

https://doi.org/10.1145/882105.882112

Published: 01 June 2003 Publication History

Abstract

Contrail processors utilize multithreading for improving energy efficiency. In Contrail, an execution of an application is divided into two streams. One is called the speculation stream. It consists of the main part of the execution and is dispatched into the fast functional units. However, several regions of the execution are skipped by utilizing trace-level value prediction. The other stream is called the verification stream. It supports the speculation stream by verifying each data prediction, and is dispatched into the slow units. The key idea is that the trace-level value prediction translates each critical path into non-critical one and moves it from the speculation stream into the verification stream, and then the non-critical instructions are executed on the slow units. In this paper, we investigate a trace-level value predictor for Contrail processors.

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Cited By

De Moura RTorres GPilla MPilla LDa Costa AFranca F(2016)Value Reuse Potential in ARM Architectures2016 28th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)10.1109/SBAC-PAD.2016.30(174-181)Online publication date: Oct-2016
https://doi.org/10.1109/SBAC-PAD.2016.30
Shimomura YKobayashi R(2012)Energy Saving of Value Prediction by Expanding Branch Target BufferIEEJ Transactions on Electronics, Information and Systems10.1541/ieejeiss.132.1706132:10(1706-1718)Online publication date: 2012
https://doi.org/10.1541/ieejeiss.132.1706
Tanaka YSato TKoushiro TGibbons PAdler M(2004)The potential in energy efficiency of a speculative chip-multiprocessorProceedings of the sixteenth annual ACM symposium on Parallelism in algorithms and architectures10.1145/1007912.1007956(273-274)Online publication date: 27-Jun-2004
https://dl.acm.org/doi/10.1145/1007912.1007956

Index Terms

A trace-level value predictor for Contrail processors
1. Hardware
  1. Hardware validation

Index terms have been assigned to the content through auto-classification.

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 31, Issue 3

June 2003

54 pages

ISSN:0163-5964

DOI:10.1145/882105

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Copyright © 2003 Authors.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 2003

Published in SIGARCH Volume 31, Issue 3

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Cited By

De Moura RTorres GPilla MPilla LDa Costa AFranca F(2016)Value Reuse Potential in ARM Architectures2016 28th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)10.1109/SBAC-PAD.2016.30(174-181)Online publication date: Oct-2016
https://doi.org/10.1109/SBAC-PAD.2016.30
Shimomura YKobayashi R(2012)Energy Saving of Value Prediction by Expanding Branch Target BufferIEEJ Transactions on Electronics, Information and Systems10.1541/ieejeiss.132.1706132:10(1706-1718)Online publication date: 2012
https://doi.org/10.1541/ieejeiss.132.1706
Tanaka YSato TKoushiro TGibbons PAdler M(2004)The potential in energy efficiency of a speculative chip-multiprocessorProceedings of the sixteenth annual ACM symposium on Parallelism in algorithms and architectures10.1145/1007912.1007956(273-274)Online publication date: 27-Jun-2004
https://dl.acm.org/doi/10.1145/1007912.1007956

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