Article

Fast hazard detection in combinational circuits

Authors:

Cheoljoo Jeong,

Steven M. NowickAuthors Info & Claims

DAC '04: Proceedings of the 41st annual Design Automation Conference

Pages 592 - 595

https://doi.org/10.1145/996566.996728

Published: 07 June 2004 Publication History

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Abstract

In designing asynchronous circuits it is critical to ensure that cir-cuits are free of hazards in the specified set of input transitions. In this paper, two new algorithms are proposed to determine if a com-binational circuit is hazard-free without exploring all its gates, thus providing more efficient hazard detection. Experimental results in-dicate that the best new algorithm on average visits only 20.7% of the original gates, with an average runtime speedup of 1.69 and best speedup of 2.27 (for the largest example.

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Cited By

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Dobai RGramatová E(2011)A novel automatic test pattern generator for asynchronous sequential digital circuitsMicroelectronics Journal10.1016/j.mejo.2010.10.01342:3(501-508)Online publication date: 1-Mar-2011
https://dl.acm.org/doi/10.1016/j.mejo.2010.10.013
Mondal AChakrabarti P(2006)Reasoning about timing behavior of digital circuits using symbolic event propagation and temporal logicIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85950825:9(1793-1814)Online publication date: 1-Sep-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.859508
Shanthi ASingaram L(2005)Evolution of Asynchronous Sequential CircuitsProceedings of the 2005 NASA/DoD Conference on Evolvable Hardware10.1109/EH.2005.23(93-96)Online publication date: 29-Jun-2005
https://dl.acm.org/doi/10.1109/EH.2005.23

Index Terms

Fast hazard detection in combinational circuits
1. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Combinational circuits

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Published In

DAC '04: Proceedings of the 41st annual Design Automation Conference

June 2004

1002 pages

ISBN:1581138288

DOI:10.1145/996566

General Chair:
Sharad Malik
Princeton University, Princeton, NJ
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Andrew B. Kahng
University of California at San Diego, La Jolla, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 June 2004

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June 7 - 11, 2004

CA, San Diego, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Dobai RGramatová E(2011)A novel automatic test pattern generator for asynchronous sequential digital circuitsMicroelectronics Journal10.1016/j.mejo.2010.10.01342:3(501-508)Online publication date: 1-Mar-2011
https://dl.acm.org/doi/10.1016/j.mejo.2010.10.013
Mondal AChakrabarti P(2006)Reasoning about timing behavior of digital circuits using symbolic event propagation and temporal logicIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85950825:9(1793-1814)Online publication date: 1-Sep-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.859508
Shanthi ASingaram L(2005)Evolution of Asynchronous Sequential CircuitsProceedings of the 2005 NASA/DoD Conference on Evolvable Hardware10.1109/EH.2005.23(93-96)Online publication date: 29-Jun-2005
https://dl.acm.org/doi/10.1109/EH.2005.23

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Technology Mapping of Speed-Independent Circuits Based on Combinational Decomposition and Resynthesis

A State Assignment Approach to Asynchronous CMOS Circuit Design