article

Introduction to the cell broadband engine architecture

Authors:

C. R. Johns,

D. A. BrokenshireAuthors Info & Claims

IBM Journal of Research and Development, Volume 51, Issue 5

Pages 503 - 519

https://doi.org/10.1147/rd.515.0503

Published: 01 September 2007 Publication History

Abstract

This paper provides an overview of the Cell Broadband Engine^™ Architecture (CBEA). The CBEA defines a revolutionary extension to a more conventional processor organization and serves as the basis for the development of microprocessors targeted at the computer entertainment, multimedia, and real-time market segments. In this paper, the organization of the architecture is described, as well as the instruction set, commands, and facilities defined in the architecture. In many cases, the motivation for these facilities is explained and examples are provided to illustrate their intended use. In addition, this paper introduces the Software Development Kit and the software standards for a CBEA-compliant processor.

References

[1]

1. Cell Broadband Engine Architecture; see http://www.ibm. com/chips/techlib/techlib.nsf/techdocs/ 1 AEEE1270EA2776387257060006E61 BA.

Google Scholar

[2]

2. J. A. Kahle, M. N. Day, H. P. Hofstee, C. R. Johns, T. R. Maeurer, and D. Shippy, "Introduction to the Cell Multiprocessor," IBM J. Res. & Dev. 49, No. 4/5, 589-604 (2005).

Digital Library

Google Scholar

[3]

3. PowerPC, Architecture Book, Version 2.02; see http:// www.ibm.com/developerworks/power/library/pa-archguidev2/.

Google Scholar

[4]

4. Synergistic Processor Unit Instruction Set Architecture; see http://www.ibm.com/chips/techlib/techlib.nsf/techdoes/ 76CA6C7304210F3987257060006F2C44.

Google Scholar

[5]

5. B. Flachs, S. Asano, S. H. Dhong, H. P. Hofstee, G. Gervais, R. Kim, T. Le, et. al., "The Microarchitecture of the Synergistic Processor for a Cell Processor," IEEE J. Solid-State Circuits 41, No. 1, 63-70 (2006).

Crossref

Google Scholar

[6]

6. D. A. Brokenshire, "Maximizing the Power of the Cell Broadband Engine Processor: 25 Tips to Optimal Application Performance"; see http://www.ibm.com/developerworks/power/ library/pa-celltipsl/.

Google Scholar

[7]

7. D. Krolak, "Just Like Being There: Papers from the Fall Processor Forum 2005: Unleashing the Cell Broadband Engine Processor: The Element Interconnect Bus"; see http:// www.ibm.com/developerworks/power/library/pa-fpfeib/ index.html.

Google Scholar

[8]

8. C. Benthin, I. Wald, M. Scherbaum, and H. Friedrich, "Ray Tracing on the Cell Processor"; see http://graphics.cs.uni-sb.de/ ~benthin/cellrt06.pdf.

Google Scholar

Cited By

View all

Saez JCastro FPrieto-Matias M(2020)Enabling performance portability of data-parallel OpenMP applications on asymmetric multicore processorsProceedings of the 49th International Conference on Parallel Processing10.1145/3404397.3404441(1-11)Online publication date: 17-Aug-2020
https://dl.acm.org/doi/10.1145/3404397.3404441
Garcia-Garcia ASaez JPrieto-Matias M(2018)Contention-Aware Fair Scheduling for Asymmetric Single-ISA Multicore SystemsIEEE Transactions on Computers10.1109/TC.2018.283641867:12(1703-1719)Online publication date: 1-Dec-2018
https://dl.acm.org/doi/10.1109/TC.2018.2836418
Liu BQiu WJiang LGong Z(2016)Software pipelining for graphic processing unit accelerationInternational Journal of High Performance Computing Applications10.1177/109434201558584530:2(169-185)Online publication date: 1-May-2016
https://dl.acm.org/doi/10.1177/1094342015585845
Show More Cited By

Index Terms

Introduction to the cell broadband engine architecture
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
2. General and reference
  1. Cross-computing tools and techniques
    1. Design

Recommendations

Cell broadband engine architecture and its first implementation: a performance view

The Cell Broadband Engine^™ (Cell/B.E.) processor is the first implementation of the Cell Broadband Engine Architecture (CBEA), developed jointly by Sony, Toshiba, and IBM. In addition to use of the Cell/B.E. processor in the Sony Computer Entertainment ...
Cell Broadband Engine Debugging for Unknown Events

Architecture and design of debugging logic for high-speed processor chips is somewhat of an art form, requiring the design of logic intended to isolate events that have not occurred. In fact, the goal is for such events never to occur, but history has ...
Massive video-surveillance parallelization on the cell broadband engine processor

The Cell Broadband Engine^®(Cell/B.E.^®) is a multicore processor with a PowerPC^®processor element (PPE) and eight synergistic processor elements (SPEs). The Cell/B.E. architecture is designed to improve upon conventional processors in terms of memory ...

Comments

Information & Contributors

Information

Published In

cover image IBM Journal of Research and Development

IBM Journal of Research and Development Volume 51, Issue 5

September 2007

129 pages

ISSN:0018-8646

Issue’s Table of Contents

Publisher

IBM Corp.

United States

Publication History

Published: 01 September 2007

Accepted: 01 March 2007

Received: 22 July 2006

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

22
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 12 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Saez JCastro FPrieto-Matias M(2020)Enabling performance portability of data-parallel OpenMP applications on asymmetric multicore processorsProceedings of the 49th International Conference on Parallel Processing10.1145/3404397.3404441(1-11)Online publication date: 17-Aug-2020
https://dl.acm.org/doi/10.1145/3404397.3404441
Garcia-Garcia ASaez JPrieto-Matias M(2018)Contention-Aware Fair Scheduling for Asymmetric Single-ISA Multicore SystemsIEEE Transactions on Computers10.1109/TC.2018.283641867:12(1703-1719)Online publication date: 1-Dec-2018
https://dl.acm.org/doi/10.1109/TC.2018.2836418
Liu BQiu WJiang LGong Z(2016)Software pipelining for graphic processing unit accelerationInternational Journal of High Performance Computing Applications10.1177/109434201558584530:2(169-185)Online publication date: 1-May-2016
https://dl.acm.org/doi/10.1177/1094342015585845
Oh JZajic APrvulovic MFensch CO'Boyle MSeznec ABodin F(2013)Traffic steering between a low-latency unswitched TL ring and a high-throughput switched on-chip interconnectProceedings of the 22nd international conference on Parallel architectures and compilation techniques10.5555/2523721.2523764(309-318)Online publication date: 7-Oct-2013
https://dl.acm.org/doi/10.5555/2523721.2523764
Chen ZQiu M(2013)SPM-aware scheduling for nested loops in CMP systemsACM SIGBED Review10.1145/2518148.251815110:2(13-13)Online publication date: 1-Jul-2013
https://dl.acm.org/doi/10.1145/2518148.2518151
Palyart MLugato DOber IBruel J(2011)Improving scalability and maintenance of software for high-performance scientific computing by combining MDE and frameworksProceedings of the 14th international conference on Model driven engineering languages and systems10.5555/2050655.2050677(213-227)Online publication date: 16-Oct-2011
https://dl.acm.org/doi/10.5555/2050655.2050677
Wang FYang CDu YChen JYi HXu W(2011)Optimizing linpack benchmark on GPU-accelerated petascale supercomputerJournal of Computer Science and Technology10.1007/s11390-011-0184-126:5(854-865)Online publication date: 1-Sep-2011
https://dl.acm.org/doi/10.1007/s11390-011-0184-1
Palyart MLugato DOber IBruel J(2011)MDE4HPCProceedings of the 15th international conference on Integrating System and Software Modeling10.1007/978-3-642-25264-8_19(247-261)Online publication date: 5-Jul-2011
https://dl.acm.org/doi/10.1007/978-3-642-25264-8_19
Hoffmann RPrell ARauber T(2010)Exploiting fine-grained parallelism on cell processorsProceedings of the 16th international Euro-Par conference on Parallel processing: Part II10.5555/1885276.1885297(175-186)Online publication date: 31-Aug-2010
https://dl.acm.org/doi/10.5555/1885276.1885297
Cho SIm DJang OSong HPaulovicks BSheinin VYeo H(2010)OpenCL and parallel primitives for digital TV applicationsIBM Journal of Research and Development10.1147/JRD.2010.206205054:5(506-519)Online publication date: 1-Sep-2010
https://dl.acm.org/doi/10.1147/JRD.2010.2062050
Show More Cited By

View Options

View options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Abstract

References

Cited By

Index Terms

Recommendations

Cell broadband engine architecture and its first implementation: a performance view

Cell Broadband Engine Debugging for Unknown Events

Massive video-surveillance parallelization on the cell broadband engine processor

Comments

Information

Published In

Publisher

Publication History

Qualifiers

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

Get Access

Login options

Full Access

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations