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The design of low noise amplifiers in deep submicron CMOS processes: a convex optimization approach

Authors:

David H. K. Hoe,

Xiaoyu JinAuthors Info & Claims

VLSI Design, Volume 2015

Article No.: 7, Page 7

https://doi.org/10.1155/2015/312639

Published: 01 January 2015 Publication History

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Abstract

With continued process scaling, CMOS has become a viable technology for the design of high-performance low noise amplifiers (LNAs) in the radio frequency (RF) regime. This paper describes the design of RF LNAs using a geometric programming (GP) optimization method. An important challenge for RF LNAs designed at nanometer scale geometries is the excess thermal noise observed in the MOSFETs. An extensive survey of analytical models and experimental results reported in the literature is carried out to quantify the issue of excessive thermal noise for short-channel MOSFETs. Short channel effects such as channel-length modulation and velocity saturation effects are also accounted for in our optimization process. The GP approach is able to efficiently calculate the globally optimum solution. The approximations required to setup the equations and constraints to allow convex optimization are detailed. The method is applied to the design of inductive source degenerated common source amplifiers at the 90 nm and 180 nm technology nodes. The optimization results are validated through comparison with numerical simulations using Agilent's Advanced Design Systems (ADS) software.

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Cited By

Ghosh SDe BKar RMandal DMal A(2019)Optimal design of a 5.5-GHz low-power high-gain CMOS LNA using the flower pollination algorithmJournal of Computational Electronics10.1007/s10825-019-01322-618:2(737-747)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1007/s10825-019-01322-6

The design of low noise amplifiers in deep submicron CMOS processes: a convex optimization approach
1. Hardware
  1. Electronic design automation
2. Networks
  1. Network types
    1. Ad hoc networks

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cover image VLSI Design

VLSI Design Volume 2015, Issue

January 2015

100 pages

ISSN:1065-514X

EISSN:1563-5171

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Hindawi Limited

London, United Kingdom

Publication History

Accepted: 30 August 2015

Revised: 21 August 2015

Received: 17 June 2015

Published: 01 January 2015

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Cited By

Ghosh SDe BKar RMandal DMal A(2019)Optimal design of a 5.5-GHz low-power high-gain CMOS LNA using the flower pollination algorithmJournal of Computational Electronics10.1007/s10825-019-01322-618:2(737-747)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1007/s10825-019-01322-6

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