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View all- Farrokhbakht HKamali HHessabi S(2017)SMARTProceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip10.1145/3130218.3130231(1-8)Online publication date: 19-Oct-2017
Applying partial power-gating to direction-sliced network-on-chip
Article No.: 45, Page 45
Abstract
Network-on-Chip (NoC) is one of critical communication architectures for futuremany-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating can be utilized in on-chip network to solve the crisis. However, the network performance is severely affected by the disconnection in the conventional power-gated NoC. In this paper, we propose a novel partial power-gating approach to improve the performance in the power-gated NoC. The approach mainly involves a direction-slicing scheme, an improved routing algorithm, and a deadlock recovery mechanism. In the synthetic traffic simulation, the proposed design shows favorable power-efficiency at low-load range and achieves better performance than the conventional power-gated one. For the application trace simulation, the design in the mesh/torus network consumes 15.2%/18.9% more power on average, whereas it can averagely obtain 45.0%/28.7% performance improvement compared with the conventional power-gated design. On balance, the proposed design with partial power-gating has a better tradeoff between performance and power-efficiency.
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- Applying partial power-gating to direction-sliced network-on-chip
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Hindawi Limited
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Publication History
Accepted: 26 July 2015
Revised: 30 June 2015
Received: 23 March 2015
Published: 01 January 2015
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View all- Farrokhbakht HKamali HHessabi S(2017)SMARTProceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip10.1145/3130218.3130231(1-8)Online publication date: 19-Oct-2017
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