Design and Optimization of Double-Tail Dynamic Latch CMOS Comparator With Modified Widlar Current Source
Abstract
References
Index Terms
- Design and Optimization of Double-Tail Dynamic Latch CMOS Comparator With Modified Widlar Current Source
Recommendations
Analysis of power for double-tail current dynamic latch comparator
The necessity of low-power, high-speed, and area proficient data converters makes dynamic cross-coupled latch based comparator more suitable for power efficiency and to maximize speed. In this paper, an investigation on the power of dynamic comparator ...
A CMOS Back-Gate Coupling LC Quadrature VCO with Switched Self-Biasing Tail Transistor Technique
In this paper, a novel complementary differential QVCO using back-gate coupling and switched self-biasing techniques is presented. Since the back-gates of the PMOS switching transistors are used as coupling terminals to achieve the quadrature outputs, ...
A 6-bit 4 MS/s, VCM-based sub-radix-2 SAR ADC with inverter type comparator
This paper presents a 6-bit sub-radix-2 redundant VCM-based SAR ADC for BLE transceiver applications. The basic trend for BLE applications is to reduce area and power consumption. In order to reduce switching power consumption, VCM-based straightforward ...
Comments
Information & Contributors
Information
Published In
Publisher
Hindawi Limited
London, United Kingdom
Publication History
Author Tags
Qualifiers
- Research-article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0