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Design and Optimization of Double-Tail Dynamic Latch CMOS Comparator With Modified Widlar Current Source

Published: 01 January 2024 Publication History

Abstract

The comparator plays a vital role in analog-to-digital converters. In the emerging communication era, these converters are useful to connect the analog field to the digital field. Also, the upcoming IoT-enabled portable devices have a requirement of energy-efficient high-speed conversions at low power consumption for a longer battery lifetime. In this paper, a double-tail dynamic latch CMOS comparator (DTDLC) with a modified Widlar current source (MWCS) has been proposed that will be suitable for high-speed applications at a low voltage and low power consumption. Use of MWCS reduces random offset voltages to avoid transistor mismatch along with the reduced power dissipation due to low operating voltage. Here, the design simulation method includes Corner analysis for power consumption and Monte Carlo histogram analysis for transistor mismatch at different random offset voltages. All the design blocks were verified and simulated by Cadence’s virtuoso schematic editor with a TSMC model file at 45-nm technology by applying 500 mV and 1 V of the supply voltage. The proposed design has a transient power consumption of 41 nW, static power consumption of 17 nW, total delay of 1 ns, and power delay product (PDP) as 17 with a FOM of 1.83 (fJ/D). By using the proposed optimized design, a total of 80% power dissipation reduction was observed. Therefore, the proposed design is more efficient in terms of metrics like delay, power, and PDP at reduced offset voltage variations and reduced effect of process variations when compared to other existing comparators. The proposed comparator circuit is also simulated and verified through layout at 45-nm CMOS process technology.

References

[1]
M. J. Pritty and M. Jhamb, “Ultra Low Power Current Mirror Design with Enhanced Bandwidth,” Microelectronics Journal, vol. 113, p. 105063, 2021.
[2]
A. Cracan and G. Bonteanu, “Wide Dynamic Range Current Mirror,” 2018 International Semiconductor Conference (CAS), pp. 173–176, 2018.
[3]
K. Monfaredi and H. Faraji Baghtash, “An Extremely Low-Voltage and High-Compliance Current Mirror,” Circuits, Systems, and Signal Processing, vol. 39, no. 1, pp. 30–53, 2020.
[4]
A. Chaudhary, “A Low Power DTMOS Based Modified Current Mirror for Improved Bandwidth Using Resistive Compensation Technique,” in 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT), pp. 1–5, Bengaluru, India, July 2018.
[5]
B. Aggarwal, M. Gupta, and A. K. Gupta, “Analysis of Low Voltage Bulk-Driven Self-Biased High Swing Cascode Current Mirror,” Microelectronics Journal, vol. 44, no. 3, pp. 225–235, 2013.
[6]
S. Rajendran, A. Chakrapani, S. Kannan, and A. Q. Ansari, “A Research Perspective on CMOS Current Mirror Circuits: Configurations and Techniques,” Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering), vol. 14, no. 4, pp. 377–397, 2021.
[7]
F. Yu, L. Gao, L. Li, K. Gu, W. Wang, and S. Cai, “A Survey on the Design of Current Comparator,” in IEEE 2nd International Conference on Electronic Information and Communication Technology (ICEICT), pp. 426–431, Xi’an, China, August 2019.
[8]
B. Chunfeng, S. Xingyue, Q. Donghai, and Z. Heming, “A Compact Low Voltage CMOS Current Mirror With High Output Resistance,” International Conference on IC Design and Technology (ICICDT), pp. 1–3, 2019.
[9]
A. Torralba, R. G. Carvajal, F. Munoz, and J. Ramirez-Angulo, “New Output Stage for Low Supply Voltage, High-Performance CMOS Current Mirrors,” in International Symposium on Circuits and Systems, ISCAS’03, Bangkok, Thailand, August 2003.
[10]
L. Safari and S. Minaei, “A Simple Low Voltage, High Output Impedance Resistor Based Current Mirror with Extremely Low Input and Output Voltage Requirements,” 39th International Conference on Telecommunications and Signal Processing (TSP), pp. 254–256, 2016.
[11]
L. Safari and S. Minaei, “A Low-Voltage Low-Power Resistor-Based Current Mirror and Its Applications,” Journal of Circuits, Systems and Computers, vol. 26, no. 1750180, pp. 1–18, 2017.
[12]
N. Mendiratta and S. L. Tripathi, “A Review on Performance Comparison of Advanced MOSFET Structures Below 45 nm Technology Node,” Journal of Semiconductors, vol. 41, no. 6, pp. 061401–061410, 2020.
[13]
T. Singh and S. L. Tripathi, “An Efficient Approach to Design a Comparator for SARADC,” 2022 IEEE VLSI Device Circuit and System (VLSI DCS), pp. 116–122, 2022.
[14]
B. Aggarwal, M. Gupta, A. K. Gupta, and S. Bansal, “A Very High Performance Compact CMOS Current Mirror,” Analog Integrated Circuits and Signal Processing, vol. 81, no. 2, pp. 367–375, 2014.
[15]
V. Savani and N. M. Devashrayee, “Analysis of Power for Double-Tail Current Dynamic Latch Comparator,” Analog Integrated Circuits and Signal Processing, vol. 100, no. 2, pp. 345–355, 2019.
[16]
P. Gupta and S. L. Tripathi, “Low Power Design of Bulk Driven Operational Transconductance Amplifier,” 2017 Devices for Integrated Circuit (DevIC), pp. 241–246, 2017.
[17]
T. Singh and S. L. Tripathi, “Design of a 16-bit 500MS/s SAR ADC for Low Power Application,” Electronic Device and Circuits Design Challenges to Implement Biomedical Applications, Elsevier, 2021.
[18]
H. P. Bakoune, E. W. Tafo, and A. M. Imano, “Design of a Low Power High-Speed Dynamic Latched Comparator in 65- Nm CMOS Using Peaking Techniques,” Analog Integrated Circuits and Signal Processing, vol. 115, no. 2, pp. 219–232, 2023.
[19]
V. Varshney and R. K. Nagaria, “Design and Analysis of Ultra High-Speed Low-Power Double Tail Dynamic Comparator Using Charge Sharing Scheme,” AEU-International Journal of Electronics and Communications, vol. 116, p. 153068, 2020.
[20]
E. Jindal, D. Singh, C. Kumar, and P. Mittal, “Low-power, High-Speed Comparator Design at 45-nm CMOS for Efficient Deep Learning Acceleration,” International Journal of Information Technology, vol. 16, no. 7, pp. 4435–4440, 2024.
[21]
M. Joy and M. Thangamani, “Design and Analysis of Low Power Comparator Using Switching Transistors,” IOSR Journal of VLSI and Signal Processing, vol. 4, no. 2, pp. 25–30, 2014.
[22]
S. Thakre and P. Srivastava, “Design and Analysis of Low-Power High-Speed Clocked Digital Comparator,” Global Conference on Communication Technologies (GCCT), pp. 650–654, 2015.
[23]
F. Kamdem, M. Crespo, W. Tafo, E. Bhuiyan, A. Cicuttin, B. Essimbi, and M. B. I. Reaz, “A Low‐offset Low‐Power and High‐speed Dynamic Latch Comparator with a Preamplifier‐Enhanced Stage, IET Circuits,” Devices & Systems, vol. 15, 2020.
[24]
V. Savani and N. M. Devashrayee, “Design and Analysis of Low-Power High-Speed Shared Charge Reset Technique Based Dynamic Latch Comparator,” Microelectronics Journal, vol. 74, pp. 116–126, 2018.
[25]
T. Singh and S. L. Tripathi, A Review of Low Power CMOS Comparator, Electronic Devices and Circuit Design Challenges and Applications in the Internet, Apple Academic Press, 2020.
[26]
J. M. Fernandes, M. K, and S. Krishna K, “Design of Double-Tail Dynamic Latch Comparator for Low Power Application,” International Conference on Intelligent Sustainable Systems (ICISS), pp. 166–170, 2019.
[27]
B. Aggarwal, M. Gupta, and A. K. Gupta, “A Comparative Study of Various Current Mirror Configurations: Topologies and Characteristics,” Microelectronics Journal, vol. 53, pp. 134–155, 2016.
[28]
B. Hart, “Designing the Widlar Current Mirror,” International Journal of Electrical Engineering Education, vol. 40, no. 4, pp. 285–298, 2003.
[29]
A. Daribay and I. N. Dolzhikova, “Widlar Current Mirror Design Using BJT-Memristor Circuits,” 2018.
[30]
T. S. Kumar and S. L. Tripathi, “Process Evaluation in FinFET Based 7T SRAM Cell,” Analog Integrated Circuits and Signal Processing, vol. 109, no. 3, pp. 545–551, 2021.
[31]
M. H. Maghami, A. M. Sodagar, and M. Sawan, “Analysis, and Design of a High-Compliance Ultra-high Output Resistance Current Mirror-Employing Positive Shunt Feedback,” International Journal of Circuit Theory and Applications, vol. 43, no. 12, pp. 1935–1952, 2015.
[32]
S. S. Baghel and D. K. Mishra, “Design and Analysis of Double-Tail Dynamic Comparator for Flash ADC’s,” International Conference on Circuits and Systems in Digital Enterprise Technology (ICCSDET), pp. 1–5, 2018.
[33]
A. Khatak, M. Kumar, and S. Dhull, “An Improved CMOS Design of Op-Amp Comparator With Gain Boosting Technique for Data Converter Circuits,” Journal of Low Power Electronics and Applications, vol. 8, no. 4, p. 33, 2018.
[34]
I. S. A. Halim, N. A. N. B. Z. Abidin, and A. A. A. Rahim, “Low Power CMOS Charge Sharing Dynamic Latch Comparator Using 0.18μm Technology,” 2011 IEEE Regional Symposium on Micro and Nano Electronics, pp. 156–160, 2011.
[35]
A. K. Singh and S. L. Tripathi, Power Analysis to Ensure Secure CMOS Architecture, Nova Publishers, 2020.
[36]
B. P. Hypolite, W. T. Evariste, and M. I. Adolphe, “A 10GHZ Low-Offset Dynamic Comparator for High-Speed and Lower-Power ADCS,” American Journal of Engineering and Applied Sciences, vol. 12, no. 2, pp. 156–165, 2019.
[37]
P. P. Gandhi and N. M. Devashrayee, “Differential Double Tail Dynamic CMOS Voltage Comparator,” International Conference on Intelligent Communication and Computational Techniques (ICCT), pp. 8–11, 2017.
[38]
T. Singh and S. L. Tripathi, “Design and Analysis of a Shared Charged Dynamic Latch Comparator,” Intelligent Circuits and Systems, pp. 384–390, CRC Press (Taylor & Francis Group), 2020.
[39]
K. S. Kumar, K. L. Krishna, K. S. Raghavendra, and K. Harish, “A High-Speed Flash Analog to Digital Converter,” in 2nd International Conference on I-SMAC (IoT in Social, Mobile, Analytics, and Cloud) (I-SMAC), pp. 283–288, 2018.
[40]
H. Oguey and D. Aebischer, “CMOS Current Reference Without Resistance,” IEEE Journal of Solid-State Circuits, vol. 32, no. 7, pp. 1132–1135, 1997.
[41]
S. Chaudhary and R. Pandey, “High-Speed, Low-Power, and Low-Offset Fully Differential Double-Tail Dynamic Comparator Using Charge Sharing Technique,” Sadhana, vol. 45, no. 1, p. 103, 2020.
[42]
N. Ghaziani, S. Radfar, Y. Bastan, P. Amiri, and M. H. Maghami, “A Low-Power Low-Voltage Dynamic Comparator in 180 nm CMOS Technology,” 28th Iranian Conference on Electrical Engineering, pp. 1–4, ICEE, 2020.
[43]
E. Jafari and M. Jafari, “Analysis the Several Techniques in Designing the Comparators for ADC Converter and Introduction the CMOS Comparator Circuit with Low Power and High Speed Suitable for Medical Equipments,” Srph Journal of Interdisciplinary Studies, vol. 2, no. 3, pp. 6–12, 2020, https://www.sid.ir/en/journal/ViewPaper.aspx?id=757301.
[44]
A. Bendali and Y. Audet, “A 1-v CMOS Current Reference with Temperature and Process Compensation,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 7, pp. 1424–1429, 2007.
[45]
S. Verma and S. L. Tripathi, “Effect of Mole Fraction and Fin Material on Performance Parameter of 14 nm Heterojunction Si1-xGex FinFET and Application as an Inverter,” Silicon, vol. 14, pp. 8793–8804, 2022.

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              cover image Journal of Electrical and Computer Engineering
              Journal of Electrical and Computer Engineering  Volume 2024, Issue
              2024
              1290 pages
              ISSN:2090-0147
              EISSN:2090-0155
              Issue’s Table of Contents
              This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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              Hindawi Limited

              London, United Kingdom

              Publication History

              Published: 01 January 2024

              Author Tags

              1. CMOS
              2. comparator
              3. dynamic latch
              4. low power
              5. Widlar current

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