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An SMT-based approach for generating trace examples and counter-examples of parametric properties

Published: 01 January 2021 Publication History
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  • Abstract

    The ParTraP language has been designed to express temporal and timed properties on finite execution traces of parametric events. It aims to ease properties' expression for users not experienced in formal methods. In this paper, we propose an approach that allows generating trace examples and counter-examples in an understandable fashion in order to help such users to better express requirements. So, ParTraP properties are mapped into a satisfiability modulo theories (SMT) context to be fed to Z3 SMT solver to check satisfaction and produce interpretations. A tool named ParTraP-EG is dedicated to that purpose. We report experiments carried out on a set of properties from an industrial case study of computer-aided surgery system.

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              cover image International Journal of Critical Computer-Based Systems
              International Journal of Critical Computer-Based Systems  Volume 10, Issue 2
              2021
              89 pages
              ISSN:1757-8779
              EISSN:1757-8787
              DOI:10.1504/ijccbs.2021.10.issue-2
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              Inderscience Publishers

              Geneva 15, Switzerland

              Publication History

              Published: 01 January 2021

              Author Tags

              1. runtime verification
              2. parametric traces
              3. temporal properties
              4. timed properties
              5. satisfiability modulo theories
              6. SMT
              7. trace examples
              8. trace counter-examples

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