Article

A Flexible Virtual Platform for Computational and Communication Architecture Exploration of DMT VDSL Modems

Authors:

Silvia Brini,

Doha Benjelloun,

Fabien CastanierAuthors Info & Claims

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2

Page 20164

Published: 08 June 2019 Publication History

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Abstract

In this paper a high-level SoC architecture exploration of DMT (Discrete Multitone) VDSL transceivers (Very high speed Digital Subscriber Line) is presented. A flexible and complete virtual platform was developed for the purpose, exploiting the paradigm of "orthogonalization of concerns" (functionality independent from architecture) in the framework of Cadence VCC system level design tool. An accurate processor model, obtained through the back-annotation of profiling results on a target DSP core, allowed the exploration of different HW/SW partitioning and the study of the computational units required. A transaction-accurate VCC bus model was developed for the investigation of the on-chip bus architecture and its relevant parameters dimensioning.

References

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{1} ETSI TS 101: Transmission and Multiplexing; Access transmission systems on metallic access cables; Very high speed Digital Subscriber Line (VDSL); Part 1: Functional Requirements (270-1 V1.2.1, 1999) & Part 2: Transceiver specification (270-2 V1.1.5, 2000).

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{2} D. J. G. Mestdagh et al. "Zipper VDSL: a solution for robust duplex communication over telephone lines". IEEE Communication Magazine, May 2000.

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{3} B. R. Wiese, J. S. Chow. "Programmable implementations of xDSL transceiver systems". IEEE Communication Magazine, May 2000.

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Cited By

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Um JKwon WHong SKim YChoi KKong JEo SKim TGielen G(2006)A systematic IP and bus subsystem modeling for platform-based system designProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131639(560-564)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131639
Hong SYoo SLee SLee SNam HYoo BHwang JSong DKim JKim JJin HChoi KKong JEo SBergamaschi RChoi K(2006)Creation and utilization of a virtual platform for embedded software optimization:Proceedings of the 4th international conference on Hardware/software codesign and system synthesis10.1145/1176254.1176311(235-240)Online publication date: 22-Oct-2006
https://dl.acm.org/doi/10.1145/1176254.1176311

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A Flexible Virtual Platform for Computational and Communication Architecture Exploration of DMT VDSL Modems

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DATE '03: Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2

March 2003

292 pages

ISBN:0769518702

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IEEE Computer Society

United States

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Published: 08 June 2019

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DATE03: Design, Automation, and Test in Europe 2003

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Um JKwon WHong SKim YChoi KKong JEo SKim TGielen G(2006)A systematic IP and bus subsystem modeling for platform-based system designProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131639(560-564)Online publication date: 6-Mar-2006
https://dl.acm.org/doi/10.5555/1131481.1131639
Hong SYoo SLee SLee SNam HYoo BHwang JSong DKim JKim JJin HChoi KKong JEo SBergamaschi RChoi K(2006)Creation and utilization of a virtual platform for embedded software optimization:Proceedings of the 4th international conference on Hardware/software codesign and system synthesis10.1145/1176254.1176311(235-240)Online publication date: 22-Oct-2006
https://dl.acm.org/doi/10.1145/1176254.1176311

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On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches

Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application

Communication architecture design for reconfigurable multimedia SoC platform

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On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches

Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application

Communication architecture design for reconfigurable multimedia SoC platform

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