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HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder

Authors:

Matjaz Verderber,

Andrej Zemva,

Damjan LampretAuthors Info & Claims

DATE '03: Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2

Page 20238

Published: 03 March 2003 Publication History

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Abstract

In this paper, we propose an optimized real-time MPEG-2 video decoder. The decoder has been implemented in one FPGA device as a HW/SW partitioned system. We made time/power-consumption analysis and optimization of the MPEG-2 decoder. On the basis of the achieved results, we decided for HW implementation of the IDCT and VLD algorithms. Remaining parts were realized in SW with 32-bit RISC processor. MPEG-2 decoder (RISC processor, IDCT core, VLD core) has been described in Verilog/VHDL and implemented in Virtex 1600E FPGA. Finally, the decoder has been tested on the Flextronics prototyping board.

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Cited By

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Clemente JBeretta IRana VAtienza DSciuto D(2014)A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable PlatformsACM Transactions on Reconfigurable Technology and Systems10.1145/26115627:2(1-27)Online publication date: 4-Jul-2014
https://dl.acm.org/doi/10.1145/2611562
Tanougast CJaniaut MBerviller YRabah HWeber SBouridane A(2009)An embedded and programmable system based FPGA for real time, MPEG stream buffer analysisIEEE Transactions on Circuits and Systems for Video Technology10.1109/TCSVT.2008.200925419:2(237-249)Online publication date: 1-Feb-2009
https://dl.acm.org/doi/10.1109/TCSVT.2008.2009254

Index Terms

HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder
1. Computing methodologies
  1. Artificial intelligence
    1. Computer vision
2. Hardware
  1. Communication hardware, interfaces and storage
  2. Very large scale integration design

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DATE '03: Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2

March 2003

292 pages

ISBN:0769518702

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IEEE Computer Society

United States

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Published: 03 March 2003

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DATE03: Design, Automation, and Test in Europe 2003

March 3 - 7, 2003

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Clemente JBeretta IRana VAtienza DSciuto D(2014)A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable PlatformsACM Transactions on Reconfigurable Technology and Systems10.1145/26115627:2(1-27)Online publication date: 4-Jul-2014
https://dl.acm.org/doi/10.1145/2611562
Tanougast CJaniaut MBerviller YRabah HWeber SBouridane A(2009)An embedded and programmable system based FPGA for real time, MPEG stream buffer analysisIEEE Transactions on Circuits and Systems for Video Technology10.1109/TCSVT.2008.200925419:2(237-249)Online publication date: 1-Feb-2009
https://dl.acm.org/doi/10.1109/TCSVT.2008.2009254

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FPGA-oriented HW/SW implementation of the MPEG-4 video decoder

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FPGA-oriented HW/SW implementation of the MPEG-4 video decoder

HW/SW Codesign of the MPEG-2 Video Decoder

FPGA implementation of a HW/SW platform for multimedia embedded systems

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